Package structure and its fabrication method

Patent metadata

Field	Value
Publication number	US-9536864-B2
Application number	US-201414445394-A
Country	US
Kind code	B2
Filing date	Jul 29, 2014
Priority date	Mar 25, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

This disclosure provides a package structure and its fabrication method. The package structure includes: a protective insulation layer; a wiring layer including at least one metal wire and disposed on the protective insulation layer; and a first package unit disposed on the wiring layer and including a plurality of metal pillars, a first integrated-circuit chip and a first molding compound layer; wherein the plural metal pillars are located in a pillar region and electrically connected to the at least one metal wire, the first integrated-circuit chip is located in a device region and electrically connected to the at least one metal wire, and the first molding compound layer filling up the remaining part of the first package unit.

First claim

What is claimed is:

1. A package structure, comprising:
a protective insulation layer;
a wiring layer, having at least one metal wire and disposed on the protective insulation layer; and
a first package unit, disposed on the wiring layer, comprising:
a plurality of metal pillars, wherein the plurality of metal pillars are located in a pillar region and electrically connected to the at least one metal wire;
a first integrated-circuit chip, located in a device region and electrically connected to the at least one metal wire;
a first molding compound layer; and
a remaining part, wherein the remaining part is a space of said first package unit not occupied by said first integrated-circuit chip and said plurality of metal pillars, and the first molding compound layer is arranged filling up the remaining part;

wherein, each of the plurality of metal pillars is a copper column; and a top surface of the metal pillars, a top surface of the first integrated-circuit chip, and a top surface of the first molding compound layer form a flat surface; said top surface of the first integrated-circuit chip is not covered by said top surface of the first molding compound layer; and said flat surface is a top surface of the first package unit.

2. The package structure of claim 1 , further comprising:
a second package unit, disposed on the top surface of the first package unit and being configured with a second integrated-circuit chip and a second molding compound layer in a manner that the second integrated-circuit chip is connected electrically to the plural metal pillars, and the second molding compound layer is arranged filling up the remaining part of the second package unit excluding the second integrated-circuit chip;
wherein, the second package unit and the first package unit are directly adjacent.

3. The package structure of claim 1 , wherein the wiring layer further comprises:
a dielectric material layer, disposed filling up the remaining part of the wiring layer excluding the at least one metal wire.

4. The package structure of claim 3 , wherein the dielectric material and the first molding compound layer are made of the same material or different materials.

5. The package structure of claim 1 , wherein the first molding compound layer is composed of a material selected from the group consisting of a novolac-based resin, an epoxy-based resin, and a silicon-based resin.

6. The package structure of claim 2 , wherein the second molding compound layer is composed of a material selected from the group consisting of a novolac-based resin, an epoxy-based resin, and a silicon-based resin.

7. The package structure of claim 1 , wherein the first integrated-circuit chip further comprises:
a plurality of first conductive pins, arranged connecting to the at least one metal wire.

8. The package structure of claim 2 , wherein the second circuit chip further comprises:
a plurality of second conductive pins, arranged connecting to the plural metal pillars.

9. The package structure of claim 1 , further comprising:
a plurality of connectors, disposed under the protective insulation layer and electrically connected to the at least one metal wire.

10. The package structure of claim 1 , wherein the first package unit consists of the first integrated-circuit chip, the plurality of metal pillars, and the remaining part filled with said first molding compound layer.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title