Simultaneous multi-page commands for non-volatile memories

Patent metadata

Field	Value
Publication number	US-9536600-B2
Application number	US-201414520403-A
Country	US
Kind code	B2
Filing date	Oct 22, 2014
Priority date	Oct 22, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the non-volatile memory device. The non-volatile memory device receives a single combined memory command for accessing the non-volatile memory. The non-volatile memory device decodes the row address and the column address for the word-line to be accessed by the single combined memory command. The non-volatile memory device accesses the word-line such that at least a most significant bit (MSB) page and a least significant bit (LSB) page are accessed simultaneously.

First claim

What is claimed is:

1. A method, in a non-volatile flash memory device comprising a non-volatile flash memory and a memory controller, for controlling an operation of the non-volatile flash memory device, the method comprising:
receiving, by the non-volatile flash memory device, a single combined memory command for accessing the non-volatile flash memory, wherein each cell of the non-volatile flash memory physically stores three or more bits per cell and has at least eight possible threshold voltage distribution states;
decoding, by the non-volatile flash memory device, a row address and a column address for a word-line to be accessed by the single combined memory command; and
accessing, by the non-volatile flash memory device, the word-line such that at least a most significant bit (MSB) page, a least significant bit (LSB) page, and at least one other significant bit page are accessed simultaneously, wherein the access to the word-line is selected from the group consisting of a programming of the word-line and a read of the word-line, wherein the programming of the word-line comprises determining, by the non-volatile flash memory device, a target voltage state for each memory cell of the word-line by accessing at least MSB data, LSB data, and at least one other significant bit of data that is to be programmed to the word-line; and programming, by the non-volatile flash memory device, each memory cell of the word-line according to the determined target voltage states, wherein the read of the word-line comprises determining, by the non-volatile flash memory device, a voltage state of each memory cell of the word-line; and reading out, by the non-volatile flash memory device, the voltage states such that at least the MSB portion of the voltage state is written to an MSB page buffer, the LSB portion of the voltage state is written to an LSB page buffer, and the at least one other significant bit portion of the voltage state is written to at least one other significant bit page buffer, and wherein the access to the word-line is selected from the group consisting of:
a full-page access to the MSB page, a half-page access to the LSB page, and full-page access to the at least one other significant bit page;
a full-page access to the MSB page, a full-page access to the LSB page, and half-page access to the at least one other significant bit page,
a full-page access to the MSB page, a half-page access to the LSB page, and half-page access to the at least one other significant bit page;
a half-page access to the MSB page, a full-page access to the LSB page, and full-page access to the at least one other significant bit page;
a half-page access to the MSB page, a half-page access to the LSB page, and full-page access to the at least one other significant bit page; and
a half-page access to the MSB page, a full-page access to the LSB page, and half-page access to the at least one other significant bit page.

2. The method of claim 1 , wherein the at least one other significant bit is a center significant bit (CSB) and wherein the programming of the word-line further comprises:
determining, by the non-volatile flash memory device, a target voltage state for each memory cell of the word-line by further accessing the center significant bit (CSB) to be programmed to the word-line; and
programming, by the non-volatile flash memory device, each memory cell of the word-line according to the determined target voltage states.

3. The method of claim 1 , wherein the at least one other significant bit is a center-high significant bit (CHSB) and a center-low significant bit (CLSB) and wherein the programming of the word-line further comprises:
determining, by the non-volatile flash memory device, a target voltage state for each memory cell of the word-line by further accessing the center-high significant bit (CHSB) and the center-low significant bit (CLSB) to be programmed to the word-line; and
programming, by the non-volatile flash memory device, each memory cell of the word-line according to the determined target voltage states.

4. The method of claim 1 , wherein the at least one other significant bit is a center significant bit (CSB), wherein the at least one other significant bit page buffer is a CSB page buffer, and wherein the read of the word-line further comprises:
reading out, by the non-volatile flash memory device, the voltage states such that the center significant bit (CSB) portion of the voltage state is written to the CSB page buffer.

5. The method of claim 1 , wherein the at least one other significant bit is a center-high significant bit (CHSB) and a center-low significant bit (CLSB), wherein the at least one other significant bit page buffer is a CHSB page buffer and a CLSB page buffer, and wherein the read of the word-line further comprises:
reading out, by the non-volatile flash memory device, the voltage states such that the center-high significant bit (CHSB) portion of the voltage state is written to the CHSB page buffer and the center-low significant bit (CLSB) portion of the voltage state is written to the CLSB page buffer.

6. The method of claim 1 , wherein the at least one other significant bit page is a center significant bit (CSB) page.

7. The method of claim 1 , wherein the at least one other significant bit page is a center-high significant bit (CHSB) page and a center-low significant bit (CLSB) page.

8. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed by a non-volatile flash memory device, causes the non-volatile flash memory device to:
receive a single combined memory command for accessing a non-volatile flash memory, wherein each cell of the non-volatile flash memory physically stores three or more bits per cell and has at least eight possible threshold voltage distribution states;
decode a row address and a column address for a word-line to be accessed by the single combined memory command; and
access the word-line such that at least a most significant bit (MSB) page, a least significant bit (LSB) page, and at least one other significant bit page are accessed simultaneously, wherein the access to the word-line is selected from the group consisting of a programming of the word-line and a read of the word-line, wherein the computer readable program to program the word-line causes the non-volatile flash memory device to determine a target voltage state for each memory cell of the word-line by accessing at least MSB data, LSB data, and at least one other significant bit of data that is to be programmed to the word-line; and program each memory cell of the word-line according to the determined target voltage states, wherein the computer readable program to read the word-line causes the non-volatile flash memory device to determine a voltage state of each memory cell of the word-line; and read out the voltage states such that at least the MSB portion of the voltage state is written to an MSB page buffer, the LSB portion of the voltage state is written to an LSB page buffer, and the at least one other significant bit portion of the voltage state is written to at least one other significant bit page buffer, and wherein the access to the word-line is selected from the group consisting of:
a full-page access to the MSB page, a half-page access to the LSB page, and full-page access to the at least one other significant bit page;
a full-page access to the MSB page, a full-page access to the LSB page, and half-page access to the at least one other significant bit page;
a full-page access to the MSB page, a half-page access to the LSB page, and half-page access to the at least one other significant bit page;
a

Assignees

• IBM

Inventors

• Kim Dongki
• Kuang Jente B
• Mukundan Janani
• Nam Gi-Joon

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title