Staggered DLL clocking on N-Detect QED to minimize clock command and delay path

Patent metadata

Field	Value
Publication number	US-9536591-B1
Application number	US-201615063229-A
Country	US
Kind code	B1
Filing date	Mar 7, 2016
Priority date	Mar 7, 2016
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus is disclosed that includes a timing circuit configured to provide an internal clock signal; a clock stagger circuit configured to receive the internal clock signal from the timing circuit and to generate at least one delayed internal clock signal; and a shift circuit arranged in a command decode and delay path of a command signal, coupled to the timing circuit and to the clock stagger circuit, and configured to capture the command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal

First claim

The invention claimed is:

1. An apparatus, comprising:
a timing circuit configured to receive an external clock signal and provide an internal clock signal;
a clock stagger circuit configured to receive the internal clock signal and provide at least one delayed internal clock signal; and
a command decode and delay path configured to receive a command, and further configured to delay the command and provide a delayed command, wherein the command decode and delay path includes a shift circuit coupled to the timing circuit and to the clock stagger circuit, and configured to receive the internal clock signal from the timing circuit and to receive the at least one delayed internal clock signal from the clock stagger circuit, the shift circuit further configured to capture the delayed command according to an external clock domain and provide the delayed command according to an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal.

2. The apparatus of claim 1 , wherein the shift circuit is configured to capture the command synchronously with the delayed internal clock signal and to speed up propagation of the command through the command decode and delay path such that the command is synchronous with the internal clock signal.

3. The apparatus of claim 2 , wherein the command becomes synchronous with the internal clock signal at least before the command exits the shift circuit.

4. The apparatus of claim 2 , wherein the command decode and delay path includes a command decoder configured to decode the command, and wherein the shift circuit is configured to speed up the propagation of the command so as to make up for a delay in the command path introduced by the command decoder.

5. The apparatus of claim 1 , wherein the shift circuit is additionally configured to delay propagation of the command to provide data at an expected time based on a specified latency.

6. The apparatus of claim 1 . wherein:
when a frequency of the external clock is above a threshold, the shift circuit captures the command synchronously with the delayed internal clock and speeds up the command such that the command is synchronous with the internal clock; and
when the frequency of the external clock is below the threshold, the shift circuit captures the command synchronously with the internal clock.

7. The apparatus of claim 1 . wherein the clock stagger circuit includes a chain of series coupled delay stages, each delay stage configured to provide an additional delay of one clock cycle.

8. The apparatus of claim 1 . wherein the shift circuit includes a multiplexer configured to selectively couple a first input or a second input to an output responsive to as specific latency, the first input configured to receive the internal clock signal and the first input coupled to an input of a delay stage, the second input coupled to an output of the delay stage.

9. The apparatus of claim 1 , wherein the timing circuit is a delay locked loop.

10. The apparatus of claim 1 . further comprising:
a signal distribution network coupled to an output of the command decode and delay path,
wherein the timing circuit is further configured to provide the internal clock signal to the signal distribution network.

11. A method of controlling signals in a memory device, comprising:
providing an internal clock signal from a delay locked loop;
receiving the internal clock signal at a clock stagger circuit;
generating at least one delayed internal clock signal at the clock stagger circuit based on the internal clock signal; and
capturing a command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal.

12. The method of claim 11 , further comprising:
capturing the command synchronously with the delayed internal clock signal; and
speeding up propagation of the command through a command decode and delay path such that the command is synchronous with the internal clock.

13. The method of claim 11 , further comprising:
delaying propagation of the command to provide data at an expected time based on a specified latency.

14. The method of claim 11 , further comprising:
when a frequency of the external clock is above a threshold, capturing the command synchronously with the delayed internal clock and speeding up the command such that the command is synchronous with the internal clock; and
when the frequency of the external clock is below the threshold, capturing the command synchronously with the internal clock.

15. An apparatus, comprising:
a memory controller configured to provide a memory read command; and
a memory configured to:
capture the command from an external clock domain into an internal clock domain synchronously with a delayed internal clock signal;
speed up propagation of the command through a shift circuit such that the command is synchronous with an internal clock; and
provide data responsive to the read command including providing data at an expected time based on a specified latency.

16. The apparatus of claim 15 , wherein the shift circuit comprises a plurality of flip-flops that are connected to a command decode and delay path of a command signal for the memory read command through a respective complex gate.

17. The apparatus of claim 16 , wherein each flip-flop of the shift circuit is additionally connected to a portion of as latency signal through the respective complex gate.

18. The apparatus of claim 16 , wherein the shift circuit further comprises a plurality of inverters configured to receive a respective loop counter value, each inverter configured to receive an output from a respective one of the flip-flops of the shift circuit.

19. The apparatus of claim 16 , wherein each complex ate comprises a AND gate configured to receive the respective loop counter value, and a NOR gate coupled to the AND gate, the NOR gate coupled to an input of a respective flip-flop.

20. The apparatus of claim 19 , wherein the internal clock is provided by a delay locked loop.

Assignees

• Micron Technology Inc

Inventors

• Kwak Jongtae

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title