Processing system with interspersed processors and communication elements having improved communication routing

Patent metadata

Field	Value
Publication number	US-9535877-B2
Application number	US-201414451900-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Jun 26, 2002
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

First claim

What is claimed is:

1. A system, comprising:
a plurality of processors, each comprising a plurality of processor ports; and
a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine;
wherein the plurality of dynamically configurable communication elements are interspersed among the plurality of processors and coupled to respective ones of the plurality of processors;
wherein each the plurality of dynamically configurable communication elements is configured to be used by at least two of the plurality of processors;
wherein, for each respective one of the processors, a first portion of the plurality of processor ports are coupled to a respective subset of the plurality of dynamically configurable communication elements and a second portion of the plurality of processor ports are directly coupled to a respective subset of the plurality of processors that are physically adjacent to the processor;
wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise a first subset of communication ports coupled to a subset of the plurality of said processors and a second subset of communication ports coupled to a second subset of the plurality of dynamically configurable communication elements; and
wherein, for each of at least a plural subset of said dynamically configurable communication elements, the first memory of a respective dynamically configurable communication element is shared among a respective subset of the processors.

2. The system of claim 1 ,
wherein, for each of the at least a plural subset of said dynamically configurable communication elements, the first memory of a respective dynamically configurable communication element is shared only among one or more neighboring dynamically configurable communication elements.

3. The system of claim 1 ,
wherein, for each of the at least a plural subset of the dynamically configurable communication elements that have four neighboring processors, the first memory is shared among the four neighboring processors.

4. The system of claim 1 ,
wherein, for each of the at least a plural subset of the dynamically configurable communication elements, the first memory operates as at least a portion of a register file for its neighboring processors.

5. The system of claim 1 ,
wherein each of at least a subset of the processors is configurable to obtain data from the first memory of different ones of the configurable communication elements.

6. The system of claim 1 ,
wherein, for each of the at least a plural subset of the dynamically configurable communication elements, the first memory stores data that is directly accessible by a processor during execution of instructions.

7. The system of claim 1 ,
wherein, for each of the at least a plural subset of the dynamically configurable communication elements, the first memory stores data that is directly accessible by each of a plurality of neighboring processors during execution of instructions.

8. The system of claim 1 ,
wherein each of at least a subset of the processors is configured to obtain data from a first memory of any of a plurality of neighboring dynamically configurable communication elements.

9. The system of claim 1 ,
wherein a first processor is configured to obtain first data from a first memory of a first dynamically configurable communication element during a first time period, and wherein the first processor is configured to obtain second data from a first memory of a second dynamically configurable communication element during a second time period.

10. The system of claim 1 ,
wherein a first processor is configured to obtain a plurality of data values from a respective subset of the plurality of dynamically configurable communication elements simultaneously.

11. The system of claim 1 ,
wherein, for each of the at least a plural subset of the dynamically configurable communication elements, the first memory is configured to provide a plurality of data values to a respective subset of the plurality of processors simultaneously.

12. The system of claim 1 ,
wherein, for each of the at least a plural subset of the dynamically configurable communication elements, the first memory is coupled to the plurality of communication ports via a plurality of access ports and includes a plurality of addressable locations; and
wherein, for each of the at least a plural subset of the dynamically configurable communication elements, the routing engine is coupled to the plurality of communication ports and configured to route data between any of the plurality of communication ports.

13. The system of claim 1 , wherein each of the at least a plural subset of the plurality of dynamically configurable communication elements further comprises a direct memory access engine coupled to the plurality of communication ports and configured to transfer data between the first memory and the plurality of communication ports.

14. The system of claim 1 ,
wherein the system is comprised on an integrated circuit, wherein the integrated circuit further comprises additional processors and additional dynamically configurable communication elements.

15. A system, comprising:
a plurality of processors, each at least a subset of the plurality of processors comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and
a plurality of dynamically configurable communication elements, each of at least a subset of the plurality of dynamically configurable communication elements comprising a plurality of communication ports, a first memory, and a routing engine;
wherein the plurality of dynamically configurable communication elements are coupled to plurality of processors and interspersed among the plurality of processors;
wherein, for a first processor, a first portion of the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements and a second portion of the plurality of processor ports are directly coupled to a respective subset of the plurality of processors that are physically adjacent to the first processor;
wherein, for a first dynamically configurable communication element, the plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements; and
wherein the memory of the first dynamically configurable communication element is shared among the first subset of the plurality of processors.

16. The system of claim 15 ,
wherein, the first subset of the plurality of processors are neighboring processors to the first dynamically configurable communication element.

17. The system of claim 15 ,
wherein each of the at least a subset of the plurality of processors is dynamically configurable to obtain data from memory of different ones of the dynamically configurable communication elements.

18. The system of claim 15 ,
wherein the first memory stores data that is directly accessible by a processor during execution of instructions.

19. The system of claim 15 ,
wherein a first processor is configured to obtain first data from the memory of the first dynamically configurable communication element during a first time period, a

Assignees

• Coherent Logix Inc

Inventors

• Doerr Michael B
• Hallidy William H
• Gibson David A
• Chase Craig M

Classifications

• G06F15/8023 Primary

  Two dimensional arrays, e.g. mesh, torus · CPC title

• Y02B60/1207

  Cross-Sectional Technologies · mapped topic

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title