Signal processing system and associated method

Patent metadata

Field	Value
Publication number	US-9535858-B2
Application number	US-201414173870-A
Country	US
Kind code	B2
Filing date	Feb 6, 2014
Priority date	Mar 7, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

The present invention provides a signal processing system and associated method. The signal processing system includes converter(s) for conversion between digital and analog, each converter includes multiple serially coupled units forming multiple frequency interfaces respectively associating with different frequencies, and each converter is partitioned, at a selected frequency interface, to a first portion and a second portion respectively formed in the first chip and the second chip. The partitioning frequency interface is selected to reduce implement cost.

First claim

What is claimed is:

1. A signal processing system distributed across a first chip and a second chip, comprising:
a first inter-chip connection circuit formed in the first chip,
a second inter-chip connection circuit formed in the second chip and coupled to the first inter-chip connection circuit, and
a quantity of converters for conversion between digital and analog;
each of the quantity of converters comprising:
a plurality of serially coupled units forming a plurality of frequency interfaces, different ones of the frequency interfaces respectively associating with different frequencies, and each of the units capable of converting frequencies between two consecutive ones of the frequency interfaces;
wherein the first inter-chip connection circuit and the second inter-chip connection circuit partition each converter to a first portion and a second portion at a corresponding one of the frequency interfaces of each converter, the first portion and the second portion of each converter are respectively formed in the first chip and the second chip, and the first inter-chip connection circuit and the second inter-chip connection circuit are arranged to relay signal between the first portion and the second portion of each converter.

2. The signal processing system of claim 1 , the quantity of converters including a digital-to-analog converter (DAC), the DAC being capable of converting a digital input signal to an analog output signal, and further comprising:
a DAC interface circuit coupled to a last of the units of the DAC, and
a DAC stage coupled to the DAC interface circuit;
wherein a first of the units of the DAC is capable of receiving the digital input signal and accordingly providing a signal of a higher sampling frequency, each of the units following the first of the units is capable of receiving a signal provided by a preceding one of the units and accordingly providing another signal of a higher sampling frequency to a successive one of the units; the DAC interface circuit is capable of modulating a signal provided by the last of the units to form a modulated signal by sigma-delta modulation, and the DAC stage is capable of converting the modulated signal to the analog output signal.

3. The signal processing system of claim 1 , the quantity of converters including an analog-to-digital converter (ADC); the ADC being capable of converting an analog input signal to a digital output signal, and further comprising:
an ADC interface circuit coupled to a first of the units of the ADC, capable of providing a second modulated signal in response to the analog input signal by sigma-delta modulation;
wherein a first of the units of the ADC is capable of receiving the second modulated signal and accordingly providing a signal of a lower sampling frequency, each of the units between the first and a last of the units is capable of receiving a signal provided by a preceding one of the units and accordingly providing another signal of a lower sampling frequency to a successive one of the units, and the last of the units is capable of receiving a signal provided by a preceding one of the units and accordingly providing the digital output signal of a lower sampling frequency.

4. The signal processing system of claim 1 , wherein:
the quantity of converters include a first number of first kind converters, each first kind converter is capable of providing a first inter-unit signal to be transferred from a first portion to a second portion of each first kind converter,
the first inter-chip connection circuit is capable of arranging samples in a first number of first inter-unit signals to form a first amount of first streams, and transmitting the first amount of first streams respectively via a same amount of first data balls of the first inter-chip connection circuit, and
the second inter-chip connection circuit is capable of receiving the first amount of first streams via a same amount of second data balls of the second inter-chip connection circuit respectively coupled to the first amount of first data balls, rearranging samples in the first amount of first streams, and accordingly obtaining the first number of first inter-unit signals for the first number of second portions of the first number of first kind converters.

5. The signal processing system of claim 4 , wherein the first inter-chip connection circuit is further capable of adding error correction information to the first amount of first streams according to the first number of first inter-unit signals, and
the second inter-chip connection circuit is further capable of correcting the received first amount of first streams in response to the error correction information while obtaining the first number of first inter-unit signals.

6. The signal processing system of claim 4 , wherein the first amount of first streams is less than the first number.

7. The signal processing system of claim 4 , wherein:
each first kind converter further comprises:
a first encoding stage in the first portion of each first kind converter, and
a first decoding stage in the second portion of each first kind converter;

wherein the first encoding stage of each first kind converter is capable of encoding the first inter-unit signal of each first kind converter to provide a first encoded signal; the first inter-chip connection circuit arranges the first number of first encoded signals of the first number of first kind converters to form the first amount of first streams, the second inter-chip connection circuit rearranges the first amount of first streams and accordingly obtains the first number of first encoded signals for the first number of second portions of the first number of first kind converters, and the first decoding stage of each first kind converter is capable of decoding an associated one of the first number of first encoded signals obtained by the second inter-chip connection circuit to obtain the first inter-unit signal for the second portion of each first kind converter.

8. The signal processing system of claim 4 , wherein:
the quantity of converters further includes a second number of second kind converters,
each second kind converter is capable of providing a second inter-unit signal to be transferred from the second portion to the first portion of each second kind converter,
the second inter-chip connection circuit is further capable of arranging samples in a second number of second inter-unit signals to form a second amount of second streams with the second amount equal to the first amount, and transmitting the second amount of second streams respectively via the first amount of second data balls, and
the first inter-chip connection circuit is further capable of receiving the second amount of second streams from the first amount of first data balls, rearranging samples in the second amount of second streams, and accordingly obtaining the second number of second inter-unit signals for the second number of first portions of the second number of second kind converters.

9. The signal processing system of claim 8 , wherein the second inter-chip connection circuit is further capable of adding second error correction information to the second amount of second streams according to the second number of second inter-unit signals, and
the first inter-chip connection circuit is further capable of correcting the received second amount of second streams in response to the second error correction information while obtaining the second number of second inter-unit signals.

10. The signal processing system of claim 8 , wherein the second amount of second streams is less than the second number.

11. The signal processing system of claim 8 , wherein:
each secon

Assignees

• Mediatek Inc

Inventors

• Yang Chien-Chung
• Chiang Chia-Feng
• Chen Chien-Ming

Classifications

• H03M3/508

  Details relating to the interpolation process · CPC title

• G06F11/1443

  Transmit or communication errors · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/50 Primary

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• G06F11/3051

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title