IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect

Patent metadata

Field	Value
Publication number	US-9535849-B2
Application number	US-50889009-A
Country	US
Kind code	B2
Filing date	Jul 24, 2009
Priority date	Jul 24, 2009
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.

First claim

What is claimed is:

1. An input/output (I/O) memory management unit (IOMMU) for controlling requests by an I/O device to a memory of a computer system, the IOMMU comprising:
control logic configured to translate an address received in a request from the I/O device, wherein in response to receiving in the request, a transaction layer protocol (TLP) packet including a process address space identifier (PASID) prefix, the control logic is configured to perform a two-level guest translation;
wherein the control logic is configured to access a set of guest page tables and a set of nested page tables to translate the address received in the request to obtain a system physical address (SPA) that corresponds to a physical page in the memory.

2. The IOMMU as recited in claim 1 , wherein the set of guest page tables includes a device table having one or more entries, wherein each entry is configured to store a pointer to a first guest translation table of the set of guest tables, and wherein the pointer comprises an SPA, which corresponds to an address space mapped by a virtual memory monitor (VMM) executing in on a processor of the computer system.

3. The IOMMU as recited in claim 2 , wherein the pointer to a first table in the set of nested page tables comprises a guest physical address (GPA) corresponding to an address space mapped by a guest operating system executing in a virtual machine (VM) on the processor.

4. The IOMMU as recited in claim 2 , wherein the address received in the request comprises a guest virtual address (GVA), wherein a GVA corresponds to an address space mapped by a guest application executing in a virtual machine (VM) on the processor, wherein the control logic is configured to translate the GVA to an SPA using the two-level guest translation.

5. The IOMMU as recited in claim 2 , wherein in response to receiving an I/O having no PASID prefix in the TLP packet, the control logic is configured to perform a one-level translation, wherein control logic is configured to access another pointer in the device table entry for the given request, wherein the another pointer comprises a pointer to a set of host translation page tables.

6. The IOMMU as recited in claim 5 , wherein at least some of the host translation page tables include entries having an SPA pointer to a next successive host translation table.

7. The IOMMU as recited in claim 1 , wherein the TLP packet comprises a packet having the prefix field, a header field, a data payload field, and an optional digest field, and wherein the TLP packet is conveyed from the I/O device to the IOMMU upon a peripheral component interconnect express (PCIe) link.

8. The IOMMU as recited in claim 1 , wherein the control logic is further configured to concatenate a subset of bits of the address received in the I/O request with the SPA that corresponds to a physical page in the memory to provide a final translation address.

9. The IOMMU as recited in claim 1 , further comprising a cache memory coupled to the control logic and configured to store completed translations.

10. The IOMMU as recited in claim 1 , wherein a pointer in a last guest page table points to a first table in the set of nested page tables.

11. A system comprising:
a processor;
a system memory coupled to the processor and configured to store translation data;
a least one I/O device configured to generate a request for accessing the system memory; and
an I/O memory management unit (IOMMU) coupled to the I/O device and to the system memory, the IOMMU includes:
control logic configured to translate an address received in the request from the I/O device, wherein in response to receiving in the request, a transaction layer protocol (TLP) packet including a process address space identifier (PASID) prefix, the control logic is configured to perform a two-level guest translation;
wherein the control logic is configured to access a set of guest page tables and a set of nested page tables to translate the address received in the request to obtain a system physical address (SPA) that corresponds to a physical page in the memory.

12. The system as recited in claim 11 , further comprising a cache memory coupled to the control logic and configured to store completed translations, wherein the control logic is configured to search the cache memory for a translation prior to performing any translations, and wherein in response to determining that a page level privilege has changed, the control logic is further configured to perform the translation obtain a final translation address.

13. The system as recited in claim 11 , wherein the memory is mapped into a plurality of address spaces including the SPA corresponding to an address space mapped by a virtual memory monitor (VMM) executing in on the processor, a guest physical address (GPA) corresponding to an address space mapped by a guest operating system executing in a virtual machine (VM) on the processor, and a guest virtual address (GVA) corresponding to an address space mapped by a guest application executing in a virtual machine (VM) on the processor.

14. The system as recited in claim 13 , wherein an I/O request including the GVA indicates the GVA by including the TLP PASID prefix, and an I/O request including the GPA indicates the GPA by omitting the TLP PASID prefix.

15. The system as recited in claim 11 , wherein the address received in the request comprises a GVA, wherein the control logic is configured to translate the GVA to an SPA using the two-level guest translation.

16. The system as recited in claim 11 , wherein the TLP packet comprises a packet having the prefix field, a header field, a data payload field, and an optional digest field, and wherein the TLP packet is conveyed from the I/O device to the IOMMU upon a peripheral component interconnect express (PCIe) link.

17. An input/output (I/O) memory management unit (IOMMU) for controlling requests by an I/O device to a memory of a computer system, the IOMMU comprising:
control logic configured to translate an address received in a request from the I/O device, wherein in response to receiving in the request, a transaction layer protocol (TLP) packet including a process address space identifier (PASID) prefix, the control logic is configured to perform a two-level guest translation using translation data stored within the memory;
wherein the translation data includes:
one or more device table entries in a device data structure; and
a first set of page data structures including a set of guest page data structures and a set of nested page data structures;

wherein the control logic is further configured to:
select a device data structure entry for a given request using a device identifier corresponding to the I/O device that generates the request;
use a pointer from the selected device data structure entry to access the set of guest translation data structures, and

use a pointer from a guest translation data structure to access the set of nested page data structures.

18. A method for controlling input/output I/O requests to a memory of a computer system using an input/output memory management unit (IOMMU), the method comprising:
storing translation data in the memory of a computer system, wherein the translation data includes a set of guest page tables and a set of nested page tables;
control logic translating an address received in a request from the I/O device, wherein in response to receiving in the request, a transaction layer protocol (TLP) packet including a process address space identifier (PASID) prefix, the control logic is co

Assignees

• Kegel Andrew G
• Hummel Mark D
• Glaser Stephen D
• Advanced Micro Devices Inc

Inventors

• Kegel Andrew G
• Hummel Mark D
• Glaser Stephen D

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/0882

  Page mode · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/063

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title

• G06F3/064

  Management of blocks · CPC title