Cache memory and cache memory control unit

Patent metadata

Field	Value
Publication number	US-9535841-B2
Application number	US-201013515315-A
Country	US
Kind code	B2
Filing date	Dec 14, 2010
Priority date	Dec 21, 2009
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221 , a valid field 222 , and a dirty field 223 . The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

First claim

The invention claimed is:

1. A cache memory comprising:
a tag storage section including a plurality of entries each including a tag address and a remaining number of times for reference, one or more entries being retrieved for reference through searching the plurality of entries by a first address segment which configures part of an access address,
wherein each of the plurality of entries includes a field indicating whether or not data in a cache line of the corresponding entry and data in a main memory are identical to each other;
a data storage section configured to store pieces of data each corresponding to the plurality of entries;
circuitry configured to:
compare a second address-segment which configures another part of the access address with the tag address included in each of the one or more of the retrieved entries, thereby to find an entry having a tag address that matches the second address-segment; and
select a piece of data corresponding to the found entry from the data storage section, in a read access,
wherein, in the read access, the circuitry is configured to invalidate the found entry without performing a write-back operation after the read access in a case that the remaining number of times for reference included in the found entry is equal to one, whereas the circuitry is configured to decrement, by one, the remaining number of times for reference included in the found entry in a case that the remaining number of times for reference is greater than one, and
wherein, upon the invalidation of the found entry, the circuitry is configured to set a value of the field to “0”.

2. The cache memory according to claim 1 , wherein upon execution of a write access, the circuitry is configured to perform control to save data to be written in the write access and the remaining number of times for reference into an external memory without accessing the data storage section, in a case that the remaining number of times for reference in each of the retrieved entries is greater than zero.

3. The cache memory according to claim 2 , further comprising a pre-fetch control section configured to perform control to prefetch the saved data and the saved remaining number of times for reference from the external memory to the data storage section and the tag storage section, respectively, in a case that the data storage section has a free space.

4. The cache memory according to claim 2 , further comprising a pre-fetch control section configured to perform control to prefetch the saved data from an external memory to the data storage section as well as to set the remaining number of times for reference in the tag storage section to one, in a case that the data storage section has a free space.

5. The cache memory according to claim 1 , further comprising:
a valid bit included in each of the plurality of entries indicating a validity of the corresponding entry,
wherein, upon the invalidation of the found entry, the circuitry is configured to set a value of the valid bit to “0”.

6. The cache memory according to claim 1 , further comprising a region designation register configured to designate a specific region in the cache memory,
wherein, upon an execution of the read access in a case that the access address belongs to the specific region, the circuitry is configured to perform control to fetch data from an external memory, and set the remaining number of times for reference to “1”.

7. A cache memory control unit comprising:
circuitry configured to:
store a plurality of entries, each including a tag address and a remaining number of times for reference, one or more entries being retrieved for reference through searching the plurality of entries by a first address segment which configures part of an access address,
wherein each of the plurality of entries includes a field indicating whether or not data in a cache line of the corresponding entry and data in a main memory are identical to each other; and
compare a second address-segment which configures another part of the access address with the tag address included in each of the one or more of the retrieved entries, thereby to find an entry having a tag address that matches the second address-segment;
wherein, in a read access,
the circuitry is configured to invalidate the found entry without performing a write-back operation after the read access in a case that the remaining number of times for reference included in the found entry is equal to one, and decrement, by one, the remaining number of times for reference included in the found entry in a case that the remaining number of times for reference is greater than one, and
wherein, upon the invalidation of the found entry, the circuitry is configured to set a value of the field to “0”.

8. A cache memory comprising:
a tag storage section including a plurality of entries each including a tag address and a time-limitation flag indicating whether or not the entry is time-limited, one or more entries being retrieved for reference through searching the plurality of entries by a first address-segment which configures part of an access address,
wherein each of the plurality of entries includes a field indicating whether or not data in cache line of the corresponding entry and data in a main memory are identical to each other;
a data storage section configured to store pieces of data each corresponding to the plurality of entries, and a remaining number of times for reference of an entry including a time-limitation flag indicating that the entry is time-limited;
circuitry configured to:
compare a second address-segment which configures another part of the access address with the tag address included in each of the one or more of the retrieved entries, thereby to find an entry having a tag address that matches the second address-segment; and
select a piece of data corresponding to the found entry from the data storage section, in a read access,
wherein, in the read access,
the circuitry is configured to invalidate the found entry without performing a write-back operation after the read access, in a case that the found entry includes a time-limitation flag indicating that the entry is time-limited and in a case that the remaining number of times for reference included in the found entry is equal to one,
the circuitry is configured to decrement, by one, the remaining number of times for reference included in the found entry, in a case that the found entry includes the time-limitation flag indicating that the entry is time-limited and in a case that the remaining number of times for reference included in the found entry is greater than one, and
wherein, upon the invalidation of the found entry, the circuitry is configured to set a value of the field to “0”.

9. The cache memory according to claim 8 , wherein upon execution of a write access, the circuitry is configured to perform control to save data to be written in the write access and the remaining number of times for reference into an external memory without accessing the data storage section in a case that the remaining number of times for reference in each of the retrieved entries is greater than zero.

10. The cache memory according to claim 9 , further comprising a pre-fetch control section configured to perform control to prefetch the saved data and the saved remaining number of times for reference from the external memory to the data storage section, in a case that the data storage section has a free space.

11. The cache memory according to claim 8 , further comprising a region designation register configured to designate a specific region on the external memory,
wherein upon execution of a write access, the circuitry is configured

Assignees

• Hirao Taichi
• Sakaguchi Hiroaki
• Yoshikawa Hiroshi
• Ishii Masaaki
• Sony Corp

Inventors

• Hirao Taichi
• Sakaguchi Hiroaki
• Yoshikawa Hiroshi
• Ishii Masaaki

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2212/314

  In storage network, e.g. network attached cache · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title