Vector processing in an active memory device

Patent metadata

Field	Value
Publication number	US-9535694-B2
Application number	US-201213569359-A
Country	US
Kind code	B2
Filing date	Aug 8, 2012
Priority date	Aug 3, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.

First claim

What is claimed is:

1. A system for vector processing in an active memory device, the system comprising:
a memory in the active memory device; and
a processing element in the active memory device, the processing element configured to perform a method comprising:
decoding, in the processing element, an instruction comprising a plurality of sub-instructions to execute in parallel;
determining an iteration count to repeat execution of the sub-instructions in parallel based on decoding an iteration count source field of the instruction that defines whether to set the iteration count based on an iteration count field of the instruction or based on an iteration count register;
repeating execution of the sub-instructions in parallel for multiple iterations, by the processing element, based on the iteration count;
accessing multiple locations in the memory in parallel based on the execution of the sub-instructions;
identifying a lane control sub-instruction in the instruction based on the decoding of the instruction, the lane control sub-instruction controlling a sequence of instruction execution and positioned in parallel with the sub-instructions to execute in parallel; and
executing the lane control sub-instruction, by the processing element, only once after execution of the sub-instructions is performed in parallel for multiple iterations.

2. The system of claim 1 , wherein the sub-instructions comprise at least a pair of a memory access sub-instruction in parallel with an arithmetic-logical sub-instruction, and the processing element is further configured to perform:
flowing the memory access sub-instruction to a load-store unit in the processing element; and
flowing the arithmetic-logical sub-instruction to an arithmetic logic unit in the processing element to execute the memory access sub-instruction in parallel with the arithmetic-logical sub-instruction.

3. The system of claim 2 , wherein the processing element is further configured to perform:
accessing one or more of: a vector computation register file and a scalar computation register file in the processing element for operands to execute the memory access sub-instruction in the load-store unit; and
accessing one or more of: the vector computation register file and the scalar computation register file in the processing element for operands to execute the arithmetic-logical sub-instruction in the arithmetic logic unit.

4. The system of claim 3 , wherein the processing element is further configured to perform:
partitioning at least one of the operands as a plurality of sub-elements based on a data type of the arithmetic-logical sub-instruction;
performing, by the arithmetic logic unit, an operation of the arithmetic-logical sub-instruction in parallel execution slots on each of the sub-elements; and
computing, by the load-store unit, an address per sub-element.

5. The system of claim 3 , wherein the processing element is further configured to perform:
flowing an output of the load-store unit to one or more of: the load-store unit, an effective-to-real address translation unit, a load-store queue, the vector computation register file, and the scalar computation register file; and
flowing an output of the arithmetic logic unit to one or more of: the arithmetic logic unit, the load-store unit, the vector computation register file, and the scalar computation register file.

6. The system of claim 3 , wherein the processing element is partitioned into multiple processing slices operable in parallel, each processing slice comprising a pair of the load-store unit and the arithmetic logic unit, and an associated pair of the vector computation register file and the scalar computation register file, and the processing element is further configured to perform:
flowing an output of the arithmetic logic unit of one processing slice to an input of one or more of: the load-store unit and the arithmetic logic unit.

7. The system of claim 3 , wherein the processing element is further configured to perform:
performing an error check on the operands prior to executing the memory access sub-instruction and the arithmetic-logical sub-instruction.

8. The system of claim 1 , wherein the lane control sub-instruction is a branch sub-instruction executed by the processing element during execution of a last iteration of the instruction based on conditions evaluated during execution of a first element of the instruction.

9. A system for vector processing in an active memory device, the system comprising:
a memory in the active memory device; and
a processing element in the active memory device, the processing element configured to perform a method comprising:
receiving, in the processing element, a command from a requestor;
fetching, in the processing element, an instruction based on the command, the instruction being fetched from an instruction buffer in the processing element;
decoding, in the processing element, the instruction comprising a plurality of sub-instructions to execute in parallel;
determining an iteration count to repeat execution of the sub-instructions in parallel based on decoding an iteration count source field of the instruction that defines whether to set the iteration count based on an iteration count field of the instruction or based on an iteration count register;
repeating execution of the sub-instructions in parallel for multiple iterations, by the processing element, based on the iteration count;
accessing multiple locations in the memory in parallel based on the execution of the sub-instructions;
identifying a lane control sub-instruction in the instruction based on the decoding of the instruction, the lane control sub-instruction controlling a sequence of instruction execution and positioned in parallel with the sub-instructions to execute in parallel; and
executing the lane control sub-instruction, by the processing element, only once after execution of the sub-instructions is performed in parallel for multiple iterations.

10. The system of claim 9 , wherein the processing element is further configured to perform:
fetching a special instruction from the instruction buffer to load a new instruction from the memory; and
replacing an entry in the instruction buffer with the new instruction based on executing the special instruction.

11. The system of claim 9 , wherein the active memory device is a three-dimensional memory cube, the memory is divided into three-dimensional blocked regions as memory vaults, and accessing multiple locations in the memory is performed through one or more memory controllers in the active memory device.

12. The system of claim 9 , wherein the sub-instructions comprise at least a pair of a memory access sub-instruction in parallel with an arithmetic-logical sub-instruction, and the processing element is further configured to perform:
flowing the memory access sub-instruction to a load-store unit in the processing element; and
flowing the arithmetic-logical sub-instruction to an arithmetic logic unit in the processing element to execute the memory access sub-instruction in parallel with the arithmetic-logical sub-instruction.

13. The system of claim 12 , wherein the processing element is further configured to perform:
accessing one or more of: a vector computation register file and a scalar computation register file in the processing element for operands to execute the memory access sub-instruction in the load-store unit; and
accessing one or more of: the vector computation register file and the scalar computation register file in the processing element for operands to execute the arithmetic-logical sub-instruction in the arithmetic

Assignees

• Fleischer Bruce M
• Fox Thomas W
• Jacobson Hans M
• Nair Ravi
• Prener Daniel A
• IBM

Inventors

• Fleischer Bruce M
• Fox Thomas W
• Jacobson Hans M
• Nair Ravi
• Prener Daniel A

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F15/8084

  Special arrangements thereof, e.g. mask or switch · CPC title

• G06F9/3879

  for non-native instruction execution, e.g. executing a command; for Java instruction set · CPC title