Temperature based flash memory system maintenance

US9535614B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9535614-B2
Application numberUS-201314086355-A
CountryUS
Kind codeB2
Filing dateNov 21, 2013
Priority dateNov 21, 2013
Publication dateJan 3, 2017
Grant dateJan 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.

First claim

Opening claim text (preview).

We claim: 1. A flash memory device comprising: a non-volatile storage having an array of memory blocks storing data; a temperature sensor adjacent the non-volatile storage; and a controller in communication with the non-volatile storage and the temperature sensor, the controller is configured for: receiving a temperature value from the temperature sensor; generating a memory maintenance queue for memory maintenance operations to be performed with the non-volatile storage, wherein the operations are organized in the queue based on priority and the priority for each of the operations is based on at least one of a time since the operation was received, a time required to finish the operation, a number of times the operation was submitted, or a priority coefficient, wherein the priority coefficient is based on historical data of maintenance operations and wherein high priority operations are performed regardless of the temperature value; and performing low priority operations when the temperature value is above a temperature threshold and during idle time. 2. The device of claim 1 wherein the priority comprises a multiplication of the time since the operation was received and the number to times the operation was submitted and the priority coefficient. 3. The device of claim 1 wherein the historical data comprises a relative amount of maintenance activity. 4. A method for scheduling memory maintenance operations in a flash memory device comprising: in a non-volatile storage device having a controller and blocks of memory, the controller: receives a temperature value; generates a memory maintenance queue for the operations to be performed on the blocks of memory, wherein the operations are organized in the queue based on a priority, wherein the priority for each of the operations is based on at least one of a time since the operation was received, a time required to finish the operation, a number of times the operation was submitted, or a priority coefficient, further wherein the priority for each operation is based on a priority coefficient and a multiplication of time since the operation was received and number of times the operation was submitted; performs lower priority operations when the temperature value is above a temperature threshold and during idle time; and performs high priority operations regardless of the temperature value. 5. The method of claim 4 wherein the temperature value is an ambient temperature of the flash memory device. 6. The method of claim 4 wherein the temperature sensor is located at a host. 7. The method of claim 4 wherein the temperature sensor is located in the non-volatile storage device and communicates with the controller. 8. The method of claim 4 wherein the priority coefficient is based on historical data of maintenance operations. 9. A flash memory device comprising: a non-volatile storage having an array of memory blocks storing data; a temperature sensor adjacent the non-volatile storage; and a controller in communication with the non-volatile storage and the temperature sensor, the controller is configured to: monitor idle time of the flash memory device; monitor a temperature of the flash memory device from the temperature sensor; and execute lower priority memory maintenance operations during the idle time and when the monitored temperature is above a temperature threshold, wherein the priority is determined based on a priority coefficient that reflects historical data of maintenance operations. 10. The flash memory device of claim 9 wherein the monitoring of the temperature comprises receiving a temperature from a temperature sensor. 11. The flash memory device of claim 10 wherein the flash memory device further comprises the temperature sensor coupled with the controller and configured to monitor the temperature and communicate the temperature to the controller. 12. The flash memory device of claim 9 wherein the controller is further configured to: execute higher priority maintenance operations regardless of the temperature. 13. The flash memory device of claim 9 wherein the controller is further configured to: receive an indication whether a power source is present; and execute lowest priority maintenance operations during the idle time and when the monitored temperature is above a temperature threshold and when the power source is present.

Assignees

Inventors

Classifications

  • Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • G11C7/04Primary

    with means for avoiding disturbances due to temperature effects · CPC title

  • using charge storage in a floating gate · CPC title

  • Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

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Frequently asked questions

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What does patent US9535614B2 cover?
A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory mai…
Who is the assignee on this patent?
Sandisk Technologies Inc, Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification G11C7/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).