Methods and apparatuses to enhance timing delay fault coverage with test logic that includes partitions and scan flip-flops

Patent metadata

Field	Value
Publication number	US-9535121-B1
Application number	US-201514792429-A
Country	US
Kind code	B1
Filing date	Jul 6, 2015
Priority date	Apr 13, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Described herein are apparatuses and methods for enhancing timing delay fault coverage during testing of functional circuitry. In one embodiment, an apparatus includes functional circuitry for performing functional operations and test logic coupled to the functional circuitry to enhance timing delay fault coverage for the functional circuitry with at-speed test sequences. The test logic includes a plurality of partitions of scan flip-flops and an independent partition scan enable input signal for each partition for enabling or disabling each partition.

First claim

What is claimed is:

1. An apparatus comprising:
functional circuitry for performing functional operations; and
test logic coupled to the functional circuitry to enhance timing delay fault coverage for the functional circuitry with at-speed test sequences, the test logic includes a plurality of partitions of scan flip-flops and an independent partition scan enable input signal for each partition for enabling or disabling each partition;
wherein the plurality of partitions are arranged in scan chains configured with alternate or adjacent flip-flops selected from first and second partitions, the test logic configured to enable the first partition and disable the second partition during a first test sequence and to disable the first partition and enable the second partition during a second test sequence, the test logic configured to enable scanning in second test data from one of the first and second partitions into the other of the first and second partitions while the other of the first and second partitions outputs first test data to a portion of the functional circuitry.

2. The apparatus of claim 1 , wherein the test logic further comprises:
override circuitry including at least one logic gate coupled to at least one scan flip-flop, each logic gate to receive a scan enable input signal and a scan override input signal while generating the partition scan enable input signal that is sent to a corresponding scan flip-flop for enabling or disabling a test mode of the scan flip-flop.

3. The apparatus of claim 1 , wherein the test logic controls stuck-at test sequences and at-speed test sequences, wherein resulting data of a stuck-at fault test sequence associated with a first clock cycle are available in the first partition and resulting data of a transition fault test sequence associated with a second clock cycle are available in the second partition.

4. The apparatus of claim 1 , wherein at least one flip-flop of the second partition temporarily acts as an extra flip-flop for storing a data value of the first partition when the first partition is enabled and the second partition is disabled for the first test sequence.

5. The apparatus of claim 1 , wherein scan chains of a design are reordered prior to fabrication of the apparatus, wherein in a reordered scan chain alternate or adjacent scan flip-flops are selected from different partitions to minimize timing delay fault testing related wiring cost and facilitate timing during a transition vector of a test sequence.

6. The apparatus of claim 1 , wherein the plurality of partitions of scan flip-flops provide vector compression by having multiple transition vectors per initialization vector with each partition corresponding to a transition vector or an initialization vector.

7. The apparatus of claim 1 , wherein the functional circuitry includes random access memory (RAM) and the plurality of partitions of scan flip-flops are capable of clocking through the RAM with transition vectors.

8. The apparatus of claim 7 , wherein multiple function clock cycles worth of RAM address, data and control values are loaded into the plurality of partitions during the initialization vector, wherein data of the RAM data is written into the RAM during a transition vector clock cycle.

9. The apparatus of claim 8 , wherein the data of the RAM is read out of the RAM during a transition vector clock cycle and this data is used as delay fault data in downstream logic cones having additional functional circuitry.

10. A method for testing functional circuitry, the method comprising:
receiving a circuit design having functional circuitry;
providing customized test logic to be embedded instrumentation for the functional circuitry, the test logic including a plurality of partitions of scan flip-flops and an independent partition scan enable input signal for each partition for enabling or disabling each partition;
segregating flip-flops of the test logic into launch and capture flip-flops, one of the first and second partitions defining the launch flip-flops, and the other of the first and second partitions defining the capture flip-flops; and
scanning in second test data from one of the first and second partitions into the launch flip-flops while launching first test data from the launch flip-flops into a portion of the functional circuitry.

11. The method of claim 10 , further comprising:
performing a test sequence with double capture clock cycles at-speed of the functional circuitry while asserting the override circuitry for the selected launch flops.

12. The method of claim 11 , wherein the test logic includes override circuitry configured to provide partial control of a transition vector (TV) of a test sequence rather than having the TV derived from an initialization vector by the functional circuitry.

13. The method of claim 10 , wherein the test logic includes override circuitry having selected scan enable circuitry.

14. The method of claim 10 , wherein the test logic includes override circuitry having selected enhanced scan circuitry or selected alternate update circuitry.

15. A computer-readable storage medium comprising executable instructions to cause a processor to perform operations, the instructions comprising:
receiving a circuit design having functional circuitry;
providing customized test logic to be embedded instrumentation for the functional circuitry, the test logic including a plurality of partitions of scan flip-flops and an independent partition scan enable input signal for each partition for enabling or disabling each partition;
segregating flip-flops of the test logic into launch and capture flip-flops, one of the first and second partitions defining the launch flip-flops, and the other of the first and second partitions defining the capture flip-flops; and

scanning in second test data from one of the first and second partitions into the launch flip-flops while launching first test data from the launch flip-flops into a portion of the functional circuitry.

16. The computer-readable storage medium of claim 15 , further comprising:
performing a test sequence with double capture clock cycles at-speed of the functional circuitry while asserting the override circuitry for the selected launch flops.

17. The computer-readable storage medium of claim 16 , wherein the test logic includes override circuitry configured to provide partial control of a transition vector (TV) of a test sequence rather than having the TV derived from an initialization vector by the functional circuitry.

18. The computer-readable storage medium of claim 15 , wherein the test logic includes override circuitry having selected scan enable circuitry.

19. The computer-readable storage medium of claim 15 , wherein the test logic includes override circuitry having selected enhanced scan circuitry or selected alternate update circuitry.

Assignees

• Abreezio LLC
• Qualcomm Inc

Inventors

• Taneja Sanjiv
• Quinton Bradley
• Hughes Andrew
• McClements Trent

Classifications

• G01R31/318558 Primary

  Addressing or selecting of subparts of the device under test · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318547

  Data generators or compressors · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title