CMOS ultrasonic transducers and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-9533873-B2
Application number	US-201414172840-A
Country	US
Kind code	B2
Filing date	Feb 4, 2014
Priority date	Feb 5, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

First claim

The invention claimed is:

1. An apparatus, comprising:
a plurality of ultrasound sources comprising a first ultrasound source, a second ultrasound source, and a third ultrasound source, wherein at least one of the first ultrasound source, second ultrasound source, or third ultrasound source is a CMOS ultrasonic transducer (CUT) comprising a first wafer having a cavity formed therein, first processing circuitry, a membrane sealing the cavity, and an electrical contact on the first wafer, the electrical contact disposed beneath a bottom side of the membrane, physically contacting the bottom side of the membrane and connecting the membrane to the first processing circuitry, the bottom side of the membrane being proximate the cavity, wherein the bottom side of the membrane and the electrical contact physically contacting the bottom side of the membrane comprise a same material;
a first ultrasound sensor and a second ultrasound sensor; and
second processing circuitry coupled to the first ultrasound sensor and the second ultrasound sensor and configured to receive and discriminate between, for each of the first and second ultrasound sensors, respective source signals emitted by the first, second, and third ultrasound sources, wherein the first ultrasound source, second ultrasound source, and the first ultrasound sensor lie in a first plane, and
wherein the second ultrasound source, the third ultrasound source, and the first ultrasound sensor lie in a second plane different than the first plane.

2. The apparatus of claim 1 , wherein the CUT comprises a plurality of cavities formed in the first wafer and sealed by the membrane.

3. The apparatus of claim 1 , wherein the CUT comprises a plurality of cavities formed in the first wafer, at least two cavities of the plurality of cavities being sealed by respective membranes.

4. The apparatus of claim 1 , wherein the first ultrasound sensor is a CUT comprising a first wafer having a plurality of cavities formed therein and a membrane sealing at least one of the cavities.

5. The apparatus of claim 4 , wherein the first wafer of the CUT of the first ultrasound sensor comprises integrated circuitry forming at least part of the processing circuitry.

6. An apparatus, comprising:
a plurality of ultrasound elements formed on a support, wherein a first ultrasound element of the plurality of ultrasound elements comprises a first wafer having a plurality of cavities formed therein and at least one membrane overlying the plurality of cavities;
a complementary metal oxide semiconductor (CMOS) circuit formed in the first wafer; and
an electrical contact on the first wafer, the electrical contact disposed beneath a bottom side of the at least one membrane, physically contacting the bottom side of the at least one membrane and connecting the at least one membrane to the CMOS circuit, the bottom side of the at least one membrane being proximate the plurality of cavities, wherein the bottom side of the at least one membrane and the electrical contact physically contacting the bottom side of the at least one membrane comprise a same material.

7. The apparatus of claim 6 , wherein each of the plurality of ultrasound elements is formed by a first wafer having a respective plurality of cavities formed therein at least one membrane overlying the respective plurality of cavities.

8. An apparatus, comprising:
opposed arrays of ultrasound elements, wherein a first array of the opposed arrays comprises a first plurality of ultrasound elements, at least two of which comprise a plurality of CMOS ultrasonic transducers, and wherein a second array of the opposed arrays comprises a second plurality of ultrasound elements, at least two of which comprise a plurality of CMOS ultrasonic transducers;
the plurality of CMOS ultrasonic transducers comprising a first wafer having a plurality of cavities formed therein and at least one membrane overlying the plurality of cavities;
a complementary metal oxide semiconductor (CMOS) circuit formed in the first wafer; and
an electrical contact on the first wafer, the electrical contact disposed beneath a bottom side of the at least one membrane, physically contacting the bottom side of the at least one membrane and connecting the at least one membrane to the CMOS circuit, the bottom side of the at least one membrane being proximate the plurality of cavities, wherein the bottom side of the at least one membrane and the electrical contact physically contacting the bottom side of the at least one membrane comprise a same material.

9. The apparatus of claim 6 , wherein the electrical contact and the bottom side of the at least one membrane comprise doped silicon.

10. The apparatus of claim 6 , wherein the electrical contact and the bottom side of the at least one membrane comprise titanium nitride.

11. The apparatus of claim 6 , wherein the ultrasonic element lacks metallization on an upper surface of the membrane distal the plurality of cavities.

12. The apparatus of claim 6 , wherein the ultrasonic element lacks an electrode on an upper surface of the membrane distal the plurality of cavities.

13. The apparatus of claim 6 , wherein the first wafer comprises a silicon substrate, and wherein the electrical contact contacts the silicon substrate.

14. The apparatus of claim 6 , wherein the electrical contact comprises a trench lined with a conductive material.

15. The apparatus of claim 14 , wherein the conductive material lining the trench is a first conductive material, and wherein the electrical contact further comprises a second conductive material at least partially filling the trench.

16. The apparatus of claim 6 , wherein the plurality of cavities is above the CMOS circuit on the first wafer.

17. The apparatus of claim 8 , wherein the first wafer comprises a silicon substrate, and wherein the electrical contact contacts the silicon substrate.

18. The apparatus of claim 8 , wherein the electrical contact comprises a trench lined with a conductive material.

19. The apparatus of claim 18 , wherein the conductive material lining the trench is a first conductive material, and wherein the electrical contact further comprises a second conductive material at least partially filling the trench.

20. The apparatus of claim 8 , wherein the plurality of cavities is above the CMOS circuit on the first wafer.

Assignees

• Butterfly Network Inc

Inventors

• Rothberg Jonathan M
• Fife Keith G
• Ralston Tyler S
• Charvat Gregory L
• Sanchez Nevada J

Classifications

• G10K9/12

  electrically operated · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B81B3/0021 Primary

  Transducers for transforming electrical into mechanical energy or vice versa (dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00) · CPC title

• B06B1/02 Primary

  making use of electrical energy (B06B1/18, B06B1/20 take precedence) · CPC title

• B06B1/0292 Primary

  Electrostatic transducers, e.g. electret-type · CPC title