Method for the local polishing of a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-9533394-B2
Application number	US-77416310-A
Country	US
Kind code	B2
Filing date	May 5, 2010
Priority date	Jun 24, 2009
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

The edge region of one side of a semiconductor wafer is polished by pressing the wafer by means of a rotatable polishing head against a polishing pad lying on a rotating polishing plate, and containing fixed abrasive. The polishing head is provided with a resilient membrane radially subdivided into a plurality of chambers by gas or liquid cushions, the polishing pressure independently selectable for each chamber. The wafer is held in position during polishing by a retainer ring pressed against the polishing pad with an application pressure, a polishing agent is introduced between the wafer and the polishing pad, and the polishing pressure exerted on the wafer in a chamber lying in the edge region of the wafer of the polishing head, and the application pressure of the retainer ring, are selected so that material is essentially removed only at the edge of the wafer.

First claim

What is claimed is:

1. A method for locally polishing one side of a semiconductor wafer, comprising pressing the semiconductor wafer by means of a rotatable polishing head against a polishing pad lying on a rotating polishing plate and containing firmly bound abrasive, wherein the polishing head is provided with a resilient membrane concentrically subdivided into a plurality of chambers individually pressurizable by means of gas or liquid cushions, and the exerted polishing pressure is independently selectable for each chamber, wherein the semiconductor wafer is held in position during polishing by a retainer ring which is also pressed against the polishing pad with an application pressure, introducing a polishing agent between the semiconductor wafer and the polishing pad, and selecting the polishing pressure exerted on the semiconductor wafer in a chamber lying in the edge region of the semiconductor wafer of the polishing head, and selecting the application pressure of the retainer ring, such that material is essentially removed only at the edge of the semiconductor wafer.

2. The method of claim 1 , wherein the polishing agent comprises an aqueous solution of the compounds sodium carbonate (Na 2 CO 3 ), potassium carbonate (K 2 CO 3 ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH) or any mixtures thereof.

3. The method of claim 2 , wherein the pH of the polishing agent solution is from 11.0 to 12.5 and the proportion of the compounds in the polishing agent solution is from 0.01 to 10 wt. %.

4. The method of claim 1 , wherein the polishing pad contains abrasive substances comprising particles of oxides of the elements cerium, aluminum, silicon or zirconium, or particles of hard substances silicon carbide, boron nitride or diamond.

5. The method of claim 1 , wherein the polishing pad contains abrasive with a particle size of 0.1-1.0 μm.

6. The method of claim 5 , wherein the polishing pad contains abrasive with a particle size of 0.1-0.6 μm.

7. The method of claim 5 , wherein the polishing pad contains abrasive with a particle size of 0.1-0.25 μm.

8. The method of claim 1 , wherein the retainer ring application pressure is 0.5-10 psi.

9. The method of claim 1 , wherein pressure in an outer chamber is higher than the pressure in an inner chamber.

10. The method of claim 1 , wherein the semiconductor wafer is a monocrystalline silicon wafer or a wafer comprising an SiGe layer, with a diameter of 300 mm or more.

11. The method of claim 1 , wherein the polishing pad has replicated microstructures on the surface of the polishing pad.

12. The method of claim 11 , wherein the replicated microstructures comprise columns with a cylindrical or polygonal cross section.

13. The method of claim 11 , wherein the replicated microstructures have the shape of pyramids or pyramid frustrums.

14. The method of claim 1 , wherein the semiconductor wafer is a donor wafer from which a transfer layer has been removed.

15. The method of claim 1 , wherein the semiconductor wafer is an SiGe wafer.

16. The method of claim 1 , wherein the semiconductor wafer has a raised step around the circumference of the wafer.

Assignees

• Schwandner Juergen
• Siltronic Ag

Inventors

• Schwandner Juergen

Classifications

• H10P90/129

  by polishing · CPC title

• H10P90/128

  by edge treatment, e.g. chamfering · CPC title

• B24B37/30

  for single side lapping of plane surfaces · CPC title

• B24B37/042 Primary

  operating processes therefor · CPC title

• H01L21/02024

  Electricity · mapped topic