Power electronics modules

Patent metadata

Field	Value
Publication number	US-9532448-B1
Application number	US-201615059465-A
Country	US
Kind code	B1
Filing date	Mar 3, 2016
Priority date	Mar 3, 2016
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A power electronics module including an insulated patterned metal substrate, a semiconductor bonded to the substrate, and an agglomeration of solid metal particles mechanically bound to each other and the substrate and arranged to form electrical interconnects between the semiconductor and a bus bar, a control board, a sensor, or a combination thereof.

First claim

What is claimed is:

1. A power electronics module comprising:
an insulated patterned metal substrate;
a semiconductor on the substrate;
an agglomeration of solid metal particles, mechanically bound to each other and the substrate, arranged to form electrical interconnects between the semiconductor and a bus bar, a control board, or a sensor; and
an additional agglomeration of solid particles, mechanically bound to each other via plastic deformation, arranged to form a dielectric between the substrate and interconnects.

2. The module of claim 1 , wherein the additional agglomeration of solid particles mechanically bound to each other and the substrate via plastic deformation is mechanically bound to the semiconductor via plastic deformation.

3. The module of claim 1 , wherein a particle-substrate interface associated with the agglomeration is free of voids and oxide inclusions.

4. The module of claim 1 , wherein the agglomeration is free of voids, oxide inclusions, or both.

5. The module of claim 1 , wherein the particles have a lenticular shape.

6. The module of claim 1 , wherein each of the particles has a discrete crystalline structure.

7. The module of claim 1 , wherein the semiconductor is a transistor or a diode.

8. A power electronics module comprising:
an insulated patterned metal substrate;
a semiconductor bonded directly to the substrate;
an agglomeration of solid metal particles mechanically bound to each other and the substrate via plastic deformation, and arranged to form a heat sink, a heat spreader, or both in thermal communication with and configured to dissipate heat generated by the semiconductor; and
an additional agglomeration of solid particles, mechanically bound to each other and the substrate via plastic deformation, arranged to form a dielectric.

9. The module of claim 8 , wherein the agglomeration comprises high thermal conductivity materials.

10. The module of claim 8 , wherein an additional agglomeration of solid metal particles mechanically bound to each other and the substrate via plastic deformation is arranged to form a high current electrical interconnect, a sensor electrical interconnect, a control electrical interconnect, or a combination thereof.

11. The module of claim 8 , wherein the dielectric prevents electrical shorting between the semiconductor and a bus bar, a control board, a sensor, or a combination thereof.

12. The module of claim 8 , wherein a particle-substrate interface associated with the agglomeration, the agglomeration, or both are free of voids, oxide inclusions, or both.

13. The module of claim 8 , wherein each of the particles has a discrete crystalline structure.

14. The module of claim 8 , wherein the semiconductor is a transistor or a diode.

15. A power electronics module comprising:
a semiconducting device bound to an insulated patterned metal substrate;
an agglomeration of solid metal particles mechanically bound to each other and the substrate via plastic deformation is arranged to form a dielectric;
an electrical interconnect embedded within the dielectric and mechanically bound to the semiconducting device via plastic deformation; and
an emitter and collector sandwiching the semiconducting device, the dielectric, and the electrical interconnect therebetween.

16. The module of claim 15 , wherein an agglomeration of solid metal particles mechanically bound to each other and the substrate via plastic deformation is arranged to form the electrical interconnect.

17. The module of claim 16 , wherein a particle-substrate interface associated with the agglomeration, the agglomeration, or both are free of voids and oxide inclusions.

18. The module of claim 15 , wherein the electrical interconnect includes a high current electrical interconnect, a sensor electrical interconnect, a control electrical interconnect, or a combination thereof.

19. The module of claim 15 , further comprising a heat sink, a heat spreader, or both.

20. The module of claim 19 , wherein the electrical interconnect, the dielectric, the heat sink, the heat spreader, or a combination thereof are deposited by cold spray or kinetic metallization.

Assignees

• Ford Global Tech Llc

Inventors

• Robert Brian Joseph

Classifications

• H10W72/07351

  characterised by changes in properties of the die-attach connectors during connecting · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title