Image processor

US9532075B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9532075-B2
Application numberUS-201414219148-A
CountryUS
Kind codeB2
Filing dateMar 19, 2014
Priority dateMar 22, 2013
Publication dateDec 27, 2016
Grant dateDec 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The image processor includes a ⅓ multiplier circuit that approximately multiplies an input value X by ⅓. The ⅓ multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.

First claim

Opening claim text (preview).

What is claimed is: 1. An image processor that derives a predetermined parameter to be included in a Network Abstraction Layer (NAL) unit packet in generating a NAL unit packet in compression coding of a moving image, the image processor comprising: a ⅓ multiplier circuit configured to approximately multiply an input value by ⅓, the ⅓ multiplier circuit including a loop operation circuit configured to repeatedly perform a predetermined operation by loops; and a setting circuit c…

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What does patent US9532075B2 cover?
The image processor includes a ⅓ multiplier circuit that approximately multiplies an input value X by ⅓. The ⅓ multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input v…
Who is the assignee on this patent?
Megachips Corp
What technology area does this patent fall under?
Primary CPC classification H04N19/13. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).