Frequency locked loop circuit
US-2024106443-A1 · Mar 28, 2024 · US
Methods related to frequency synthesis control
US9531392B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9531392-B2 |
| Application number | US-201514663336-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 19, 2015 |
| Priority date | Apr 26, 2012 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
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Abstract
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Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for controlling a frequency synthesizer of a wireless device, the method comprising: receiving, by a phase detector, a reference signal and a feedback signal; generating a current signal based at least in part on a phase difference between the reference signal and the feedback signal; performing a logic operation between a signal representative of the phase difference and a switch signal to generate a charge signal; charging, by a charge pump,…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9531392B2 cover?
- Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configu…
- Who is the assignee on this patent?
- Skyworks Solutions Inc
- What technology area does this patent fall under?
- Primary CPC classification H03L7/085. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).