Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits

Patent metadata

Field	Value
Publication number	US-9531384-B1
Application number	US-201514955898-A
Country	US
Kind code	B1
Filing date	Dec 1, 2015
Priority date	Dec 1, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An adiabatic dynamic differential logic circuit is provided for mitigating a differential power analysis (DPA) attack on a secure integrated chip including a plurality of transistors configured to perform each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit. In one embodiment, a high-performance adiabatic dynamic differential logic circuit is provided which is optimized for very high operating frequencies. In another embodiment, a body-biased adiabatic dynamic differential logic circuit is provided which utilizes transistor body biasing to improve the switching time and differential power of the design.

First claim

What is claimed is:

1. A logic circuit for mitigating a differential power analysis (DPA) attack on a secure integrated chip, the logic circuit comprising:
a plurality of transistors configured to perform each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit; and
wherein A, B and C are control signals and wherein the two-input logical output calculations of the logic circuit include:
P=A′, P′=A, Q = ( A+B )⊕ C , Q ′=( A+B )⊕ C, R= AB⊕C and R′=AB⊕C.

2. The logic circuit of claim 1 , wherein the plurality of two-input logical output calculations include AND, NAND, OR, NOR, XOR, and XOR.

3. The logic circuit of claim 1 , wherein each of the plurality of transistors has a gate node, a drain node and a source node coupled to an input node or to an output node of the logic circuit.

4. The logic circuit of claim 1 , wherein the logic circuit is physically bijective.

5. The logic circuit of claim 1 , wherein the logic circuit is logically bijective.

6. The logic circuit of claim 1 , wherein the plurality of transistors are CMOS transistors.

7. The logic circuit of claim 1 , wherein the plurality of transistors further comprise a plurality of complimentary NMOS and PMOS transistors.

8. The logic circuit of claim 1 , wherein each of the plurality of transistors has a nominal threshold voltage of approximately 0.8V.

9. The logic circuit of claim 1 , wherein each of the plurality of transistors has a nominal threshold voltage of approximately 0.5V.

10. The logic circuit of claim 1 , wherein the secure integrated chip comprises at least one cryptographic algorithm.

11. The logic circuit of claim 1 , wherein the secure integrated chip is integrated into a smart card.

12. A secure integrated chip comprising:
a logic circuit for mitigating a differential power analysis (DPA) attack on a secure integrated chips, the logic circuit comprising;
a plurality of transistors configured to perform each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit;
wherein A, B and C are control signals and wherein the two-input logical output calculations of the logic circuit include:
P=A′, P′=A, Q = ( A+B )⊕ C , Q ′=( A+B )⊕ C, R= AB⊕C and R′=AB⊕C ; and

a memory module for storing at least one cryptographic algorithm.

13. The logic circuit of claim 12 , wherein the plurality of two-input logical output calculations include AND, NAND, OR, NOR, XOR, and XOR.

14. The logic circuit of claim 12 , wherein each of the plurality of transistors has a gate node, a drain node and a source node coupled to an input node or to an output node of the logic circuit.

15. The logic circuit of claim 12 , wherein the plurality of transistors further comprise a plurality of complimentary NMOS and PMOS transistors.

16. The logic circuit of claim 12 , wherein each of the plurality of transistors has a nominal threshold voltage of approximately 0.8V.

17. The logic circuit of claim 12 , wherein each of the plurality of transistors has a nominal threshold voltage of approximately 0.5V.

18. The logic circuit of claim 12 , wherein the logic circuit is logically bijective and physically bijective.

19. A method for mitigating a differential power analysis (DPA) attack on a secure integrated chip, the method comprising:
configuring a plurality of transistors of a logic circuit on a secure integrated chip to have a gate node, a drain node and a source node of each of the plurality of transistors coupled to an input node or to an output node of the logic circuit; and
performing, with the logic circuit, each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit, wherein A, B and C are control signals and wherein the two-input logical output calculations of the logic circuit include:
P=A′, P′=A, Q = ( A+B )⊕ C , Q ′=( A+B )⊕ C, R= AB⊕C and R′=AB⊕C.

20. The method of claim 19 , wherein the plurality of two-input logical output calculations include AND, NAND, OR, NOR, XOR, and XOR.

Assignees

• Morrison Matthew
• Ligatti Jarred Adam
• Ranganathan Nagarajan
• Univ South Florida

Inventors

• Morrison Matthew
• Ligatti Jarred Adam
• Ranganathan Nagarajan

Classifications

• H03K19/0019 Primary

  by energy recovery or adiabatic operation · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title