Signal generating system and signal generating method

Patent metadata

Field	Value
Publication number	US-9531358-B2
Application number	US-201514685607-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Oct 27, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.

First claim

What is claimed is:

1. A signal generating system for generating an output signal with a 50% duty cycle, comprising:
a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equal to M based on an input signal, wherein M is a positive integer; and
a signal combining module, for combining at least two of the frequency divided signals, or combining the input signal and one of the frequency divided signals to generate at least one output combined signal;
wherein the signal generating system generates the output signal based on the output combined signal;
wherein the frequency dividing module cooperates with the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein N is a positive integer.

2. The signal generating system of claim 1 , wherein the signal combining module directly outputs the output combined signal as the output signal.

3. The signal generating system of claim 1 , wherein the frequency dividing module comprises M level triggering devices to generate M frequency divided signals, wherein M equals 2*(N.5).

4. The signal generating system of claim 1 , further comprising:
a duty cycle calibrating circuit, for adjusting a duty cycle of the output combined signal to generate the output signal.

5. The signal generating system of claim 4 , wherein the duty cycle calibrating circuit comprises:
a comparator, for comparing a duty cycle for the output signal and a duty cycle for an inverted output signal, to generate a comparing result;
a first duty cycle calibrating module, for calibrating a duty cycle of the output signal according to the comparing result; and
a second duty cycle calibrating module, for calibrating a duty cycle for the inverted output signal according to the comparing result.

6. The signal generating system of claim 5 ,
wherein the first duty cycle calibrating module comprises:
a first falling time tuning circuit, for receiving the output combined signal to generate a first adjusted output combined signal;
a buffer, for buffering the first adjusted output combined signal to generate the output signal;
wherein the second duty cycle calibrating module comprises:
a first inverter, for receiving an inverted output combined signal;
a second falling time tuning circuit, for receiving an output from the first inverter to generate a second adjusted output combined signal; and
a second inverter, for inverting the second adjusted output combined signal to generate the inverted output signal.

7. The signal generating system of claim 6 , wherein the first falling time tuning circuit comprises:
a third inverter, receiving the output combined signal;
a transistor of second type, comprising a first terminal coupled to a first voltage level, a second terminal, and a control terminal coupling to an output terminal of the third inverter;
a first transistor of first type, comprising a first terminal coupled to the second terminal of the transistor of second type, a second terminal, and a control terminal coupling to the output terminal of the third inverter;
a second transistor of first type, comprising a first terminal coupled to the second terminal of the first transistor of first type, a second terminal coupled to a second voltage level, and a control terminal.

8. The signal generating system of claim 6 , wherein the second falling time tuning circuit comprises:
a fourth inverter, receiving the output from the first inverter;
a transistor of second type, comprising a first terminal coupled to a first voltage level, a second terminal, and a control terminal coupling to an output terminal of the fourth inverter;
a first transistor of first type, comprising a first terminal coupled to the second terminal of the transistor of second type, a second terminal, and a control terminal coupling to the output terminal of the fourth inverter;
a second transistor of first type, comprising a first terminal coupled to the second terminal of the first transistor of first type, a second terminal coupled to a second voltage level, and a control terminal.

9. The signal generating system of claim 5 ,
wherein the first duty cycle calibrating module comprises:
a first inverter, for receiving the output combined signal;
a second first rising time tuning circuit, for receiving an output from the first inverter to generate a first adjusted output combined signal; and
an second inverter, for inverting the first adjusted output combined signal to generate the output signal;
wherein the second duty cycle calibrating module comprises:
a second rising time tuning circuit, for receiving an inverted output combined signal to generate a second adjusted output combined signal; and
a buffer, for buffering the second adjusted output combined signal to generate the inverted output signal.

10. The signal generating system of claim 5 ,
wherein the first duty cycle calibrating module comprises:
a first falling time tuning circuit, for receiving the output combined signal to generate a first adjusted output combined signal;
a buffer, for buffering the first adjusted output combined signal to generate the output signal;
wherein the second duty cycle calibrating module comprises:
a first rising time tuning circuit, for receiving an inverted output combined signal to generate a second adjusted output combined signal; and
a buffer, for buffering the second adjusted output combined signal to generate the inverted output signal.

11. The signal generating system of claim 5 ,
wherein the first duty cycle calibrating module comprises:
a first inverter, for receiving the output combined signal;
a first rising time tuning circuit, for receiving an output from the first inverter of the first duty cycle calibrating module to generate a first adjusted output combined signal; and
a second inverter, for inverting the first adjusted output combined signal to generate the output signal;
wherein the second duty cycle calibrating module comprises:
a third inverter, for receiving an inverted output combined signal;
a first falling time tuning circuit, for receiving an output from the third inverter of the second duty cycle calibrating module to generate a second adjusted output combined signal; and
a fourth inverter, for inverting the second adjusted output combined signal to generate the inverted output signal.

12. The signal generating system of claim 1 , wherein the signal combining module comprises an XOR circuit for performing an XOR operation to the output combined signal to generate the output signal.

13. The signal generating system of claim 1 , wherein the signal combining module comprises a signal combining module for combining at least two of the frequency divided signals to generate the output combined signal at an output terminal, wherein the signal combining module comprises:
a first initial combining circuit, for receiving a plurality of the frequency divided signals to generate a first output combined signal;
a second initial combining circuit, for receiving a plurality of the frequency divided signals to generate a second output combined signal;
a first edge calibrating device, coupled between a first voltage level and the first initial combining circuit; and
a second edge calibrating device, coupled between a second voltage level and the second initial combining circuit;
wherein the first edge calibrating device and the second edge calibrating device integrate at least one edge of the first output combined signal and the second output combined signal to generate the output comb

Assignees

• Mediatek Inc

Inventors

• Tseng Sheng-Che
• Wang Yao-Chi

Classifications

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K5/06 Primary

  by the use of delay lines or other analogue delay elements · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K3/283 Primary

  Stabilisation of output {, e.g. using crystal} · CPC title