Method and circuitry for cmos transconductor linearization
US-2016134240-A1 · May 12, 2016 · US
Method and circuitry for CMOS transconductor linearization
US9531335B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9531335-B2 |
| Application number | US-201514818882-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 5, 2015 |
| Priority date | Nov 11, 2014 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
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Abstract
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Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second-order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor.
First claim
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What is claimed is: 1. A CMOS (complementary metal oxide semiconductor) transconductor circuit comprising: (a) a first CMOS inverter including a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive a first input signal, drains of the first N-channel transistor and first P-channel transistor being coupled to a first output conductor; (b) a first degeneration element coupled…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H03F3/193Primary
Electricity · mapped topic
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- What does patent US9531335B2 cover?
- Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resisto…
- Who is the assignee on this patent?
- Texas Instruments Inc
- What technology area does this patent fall under?
- Primary CPC classification H03F3/193. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).