Power supply controller with minimum-sum multi-cycle modulation

Patent metadata

Field	Value
Publication number	US-9531279-B2
Application number	US-201414220513-A
Country	US
Kind code	B2
Filing date	May 5, 2014
Priority date	Sep 23, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An example power supply controller includes a signal separator circuit that generates a feedback signal. An error signal generator generates an error signal in response to the feedback signal. A control circuit generates a drive signal in response to the error signal. The drive signal controls switching of a switch. A multi-cycle modulation circuit is included in the control circuit and generates a skip signal in response to a start skip signal, a stop skip signal and a skip mask signal. The skip mask signal is generated in response to the skip signal. The start skip and stop skip signals cause the drive signal to start skipping or stop skipping, respectively, on-time intervals of cycles. The skip mask signal disables the start skip signal from causing the drive signal to start skipping the on-time intervals of cycles.

First claim

What is claimed is:

1. A power supply controller configured to regulate an output of a power supply by enabling and disabling switching periods defined by an oscillator, the power supply controller comprising:
an error signal generator coupled to generate an error signal in response to a feedback signal and a reference signal;
a multi-cycle modulation circuit coupled to respond to a first disabled switching period by generating a skip mask signal, which when active defines a skip mask having a duration of a first number of switching periods,
wherein while the skip mask signal is active the power supply is allowed to transition from the first or another disabled switching period to an enabled switching period, and
wherein while the skip mask signal is active the power supply is prevented from transitioning from an enabled switching period to a disabled switching period; and

a control circuit that includes the multi-cycle modulation circuit, wherein the control circuit is coupled to generate a drive signal in response to the error signal, wherein the control circuit is coupled to generate:
at relatively higher loads, a pulse width modulated drive signal with varying on-time, and
at relatively lighter loads, the drive signal with a fixed on-time and a fixed switching period.

2. The power supply controller of claim 1 , wherein the multi-cycle modulation circuit is coupled to generate the skip mask signal only in response to the first disabled switching period that is a duration greater than the first number of switching periods from a previously generated skip mask signal.

3. The power supply controller of claim 1 , further comprising a signal separator configured to extract a sensed input voltage and a sensed output voltage from a voltage on a bias winding.

4. The power supply controller of claim 1 , wherein the control circuit is further coupled to generate:
at relatively higher loads, a peak current pulse width modulation drive signal with a fixed frequency, and
at relatively lighter loads, the drive signal with a fixed frequency and a fixed peak current.

5. The power supply controller of claim 1 , wherein the control circuit is further coupled to generate:
at relatively higher loads, a period modulated drive signal, and
at relatively lighter loads, the drive signal with a fixed frequency.

6. The power supply controller of claim 1 , wherein the multi-cycle modulation circuit further comprises:
a latch to output the skip mask signal when set; and
a counter coupled to be clocked in response to a clock signal output by the oscillator, wherein the clock signal defines the switching periods and the counter is coupled to reset the latch in response to counting the first number of switching periods.

7. The power supply controller of claim 1 , wherein the control circuit includes a current limit circuit coupled to generate a variable current limit signal to regulate the output of the power supply, the current limit circuit coupled to terminate an on-time interval of each cycle of the drive signal in response to a current sense signal and the variable current limit signal.

Assignees

• Power Integrations Inc

Inventors

• Mao Mingming

Classifications

• Y02B70/16

  Cross-Sectional Technologies · mapped topic

• H02M2001/0035

  Electricity · mapped topic

• H02M3/33523 Primary

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H02M1/0035

  using burst mode control · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title