Software configurable accessories for an automatic transfer switch (ats)
US-2024111499-A1 · Apr 4, 2024 · US
US9531215B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9531215-B2 |
| Application number | US-201213425278-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 20, 2012 |
| Priority date | Jul 31, 2004 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An automatic transfer switch for a power system receiving multiple alternating current sources and delivering multiple alternating current output is described. A transfer switch control circuit can sense a power loss in one or both AC sources. Each power supply can deliver current to drive a load but, if one of the power supplies fails, the other can supply power to drive both loads.
Opening claim text (preview).
What is claimed is: 1. A transfer switch with arc suppression circuitry, the transfer switch comprising: at least one microprocessor; a first solid state switch and a first relay in parallel, wherein the at least one microprocessor is in switch control communication with the first solid state switch and the first relay, and wherein the first solid state switch and the first relay are connectable to a first outlet; a first power source input connectable to a first power source, the first power source input in power supply communication with the first solid state switch and the first relay; a second solid state switch and a second relay in parallel, wherein the at least one microprocessor is in switch control communication with the second solid state switch and the second relay, and wherein the second solid state switch and the second relay are connectable to the first outlet; a second power source input connectable to a second power source, the second power source input in power supply communication with the second solid state switch and the second relay; and a non-transitory memory having instructions stored thereon that when executed by the at least one microprocessor cause the at least one microprocessor, upon detection of an interruption in the first power source to the first power source input resulting in a disruption of power to the first outlet, to switch the first outlet over to the second power source input that was not previously supplying power to the first outlet by: activating the first solid state switch to shunt current around the first relay while opening the first relay; activating the second solid state switch while closing the second relay to supply power from the second power source to the first outlet through the second solid state switch; and deactivating the first and second solid state switches so that the second relay channels power to the first outlet. 2. The transfer switch of claim 1 , wherein the first and second solid state switches are triacs. 3. The transfer switch of claim 1 , further comprising: a third solid state switch and a third relay in parallel, wherein the at least one microprocessor is in switch control communication with the third solid state switch and the third relay, and wherein the third solid state switch and the third relay are connectable to a second outlet; a fourth solid state switch and a fourth relay in parallel, wherein the at least one microprocessor is in switch control communication with the fourth solid state switch and the fourth relay, and wherein the fourth solid state switch and the fourth relay are connectable to the second outlet. 4. The transfer switch of claim 3 , wherein the third and fourth solid state switches are triacs. 5. A transfer switch with arc suppression circuitry, the transfer switch comprising: a first power source input configured to receive power from a first power source; a second power source input configured to receive power from a second power source; a first relay; a second relay; a first solid state switch in parallel with the first relay, wherein the first relay is electrically connected to the first power source input and initially, when in a first position, is operative to direct power from the first power source input to one or more outlets; a second solid state switch in parallel with the second relay, wherein the second relay is electrically coupled with the second power input and the one or more outlets; means for automatically monitoring for interruptions in the first power source; and at least one microprocessor programmed to control the first and second solid state switches and the first and second relays, wherein in response to an interruption of power from the first power source to the first power source input, the at least one microprocessor is further programmed to: cause the first solid state switch to energize; cause the first relay to switch from the first position to a second position; and cause the second solid state switch to energize, thereby allowing the second solid state switch to provide the power received by the second power input to the one or more outlets. 6. The transfer switch of claim 5 , further comprising a first electrical load initially configured to receive power from the first power source through one of the first solid state switch and the first relay. 7. The transfer switch of claim 1 , wherein the non-transitory memory has instructions stored thereon that when executed by the at least one microprocessor further cause the at least one microprocessor to confirm that the first relay is opened before deactivating the first solid state switch. 8. The arc suppression circuit of claim 7 , wherein the non-transitory memory has instructions stored thereon that when executed by the at least one microprocessor further cause the at least one microprocessor to confirm that the second relay is closed before deactivating the second solid state switch. 9. The transfer switch of claim 1 , wherein the first power source and the second power source are two different phases of a three phase power source. 10. A power distribution unit comprising: a housing; a first power input and a second power input each penetrating the housing; a plurality of power outlets disposed on a surface of the housing; and circuitry enclosed in the housing interconnecting the first power input and the second power input with the plurality of power outlets, wherein the circuitry includes a transfer switch having an arc suppression circuit, the transfer switch comprising: at least one processing device; a first solid state switch and a first relay in parallel, wherein the at least one processing device is communicably coupled with the first solid state switch and the first relay, and wherein the first solid state switch and the first relay are connectable to the plurality of power outlets; a first power source input connectable to the first power input, the first power source input in power supply communication with the first solid state switch and the first relay; a second solid state switch and a second relay in parallel, wherein the at least one processing device is communicably coupled with the second solid state switch and the second relay, and wherein the second solid state switch and the second relay are connectable to the plurality of power outlets; a second power source input connectable to the second power input, the second power source input in power supply communication with the second solid state switch and the second relay; and a non-transitory memory having instructions stored thereon that when executed by the at least one processing device cause the at least one processing device, upon detection of an interruption in power supplied through the first power input, to: temporarily activate the first solid state switch to shunt current around the first relay while opening the first relay; temporarily activate the second solid state switch while closing the second relay to supply power from a second power source through the second power input; and deactivate the first and second solid state switches so that the second power source is providing power through the second relay to the plurality of power outlets. 11. The power distribution unit of claim 10 , further comprising a communication port to communicate information to, or receive information from, other devices. 12. The power distribution unit of claim 10 , wherein the first and second solid state switches are triacs. 13. The power distribution unit of claim 10 , further comprising at least one selection device allowing a user to select a nominal voltage range for a
Electronic means for switching from one power supply to another power supply, e.g. to avoid parallel connection · CPC title
Load break switches · CPC title
with automatic change-over {, e.g. UPS systems} · CPC title
Application transfer; between utility and emergency power supply · CPC title
Cross-Sectional Technologies · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.