Normally on high voltage switch

Patent metadata

Field	Value
Publication number	US-9530885-B2
Application number	US-201514736197-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jul 18, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies.

First claim

What is claimed is:

1. A normally on high voltage switch device (“normally on switch device”), comprising:
a first semiconductor layer of a first conductivity type, the first semiconductor layer being heavily doped and forming a drain region of the normally on switch device;
a second semiconductor layer of the first conductivity type formed on the first semiconductor layer;
a first trench and a second trench formed spaced apart in the second semiconductor layer, each of the first trench and the second trench being lined with an insulating layer and filled with a conductive material to form a trench gate of the normally on switch device;
a first doped region of a second conductivity type, opposite the first conductivity type, formed under the first trench in the second semiconductor layer and a third doped region of the second conductivity type formed under the second trench in the second semiconductor layer, the first and third doped regions being electrically connected to the conductive material in the respective first and second trenches to form a gate terminal of the normally on switch device; and
a second doped region of the first conductivity type formed on a first surface of the second semiconductor layer between the first and second trenches, the second doped region being heavily doped and forming a source region of the normally on switch device,
wherein the normally on switch device comprises a channel formed in the second semiconductor layer between the source region and the drain region and the channel has a width controlled by the gate terminal formed by the trench gate and the first and third doped regions, and in response to a reverse bias voltage being applied to the gate terminal relative to the source region, a depletion region is formed at the junction of the first and third doped regions and the second semiconductor layer to modulate the width of the channel and to pinch off the channel to switch off the normally on switch device.

2. The normally on switch device of claim 1 , further comprising:
a trench sidewall doped region of the second conductivity type formed along the sidewall of each of the first trench and second trench and in physical and electrical contact with the respective first doped region and third doped region; and
a first conductive electrode formed in electrical contact with the trench gate and the trench sidewall doped region, the conductive electrode forming the gate terminal of the normally on switch device.

3. The normally on switch device of claim 2 , wherein the trench sidewall doped region comprises a plurality of trench sidewall doped region formed spaced apart along a length of the first trench and along a length of the second trench.

4. The normally on switch device of claim 2 , wherein the trench sidewall doped region is spaced apart from the second doped region.

5. The normally on switch device of claim 1 , wherein each of the first trench and second trench is lined with a silicon oxide layer and filled with a polysilicon layer.

6. The normally on switch device of claim 1 , further comprising:
a second conductive electrode formed in electrical contact with the second doped region, the second conductive electrode forming a source terminal.

7. The normally on switch device of claim 1 , further comprising:
a third conductive electrode formed in electrical contact with the first semiconductor layer, the third conductive electrode forming a drain terminal.

8. The normally on switch device of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

9. A method for forming a normally on high voltage switch device (“normally on switch device”), comprising:
providing a first semiconductor layer of a first conductivity type, the first semiconductor layer being heavily doped and forming a drain region of the normally on switch device;
providing a second semiconductor layer of the first conductivity type formed on the first semiconductor layer;
forming a first trench and a second trench being spaced apart in the second semiconductor layer, each of the first trench and the second trench being lined with an insulating layer and filled with a conductive material to form a trench gate of the normally on switch device;
forming a first doped region of a second conductivity type, opposite the first conductivity type, under the first trench in the second semiconductor layer and forming a third doped region of the second conductivity type under the second trench in the second semiconductor layer, the first and third doped regions being electrically connected to the conductive material in the respective first and second trenches to form a gate terminal of the normally on switch device; and
forming a second doped region of the first conductivity type on a first surface of the second semiconductor layer between the first and second trenches, the second doped region being heavily doped and forming a source region of the normally on switch device,
wherein the normally on switch device comprises a channel formed in the second semiconductor layer between the source region and the drain region and the channel has a width controlled by the gate terminal formed by the trench gate and the first and third doped regions, and in response to a reverse bias voltage being applied to the gate terminal relative to the source region, a depletion region is formed at the junction of the first and third doped regions and the second semiconductor layer to modulate the width of the channel and to pinch off the channel to switch off the normally on switch device.

10. The method of claim 9 , further comprising:
forming a trench sidewall doped region of the second conductivity type along the sidewall of each of the first trench and second trench and in physical and electrical contact with the respective first doped region and third doped region; and
forming a first conductive electrode in electrical contact with the trench gate and the trench sidewall doped region, the conductive electrode forming the gate terminal of the normally on switch device.

11. The method of claim 10 , wherein forming a trench sidewall doped region comprises:
forming a plurality of trench sidewall doped region spaced apart along a length of the first trench and along a length of the second trench.

12. The method of claim 10 , wherein forming a trench sidewall doped region comprises:
forming the trench sidewall doped region spaced apart from the second doped region.

13. The method of claim 9 , further comprising:
lining each of the first trench and second trench with a silicon oxide layer and filling each of the first trench and second trench with a polysilicon layer.

14. The method of claim 9 , further comprising:
forming a second conductive electrode in electrical contact with the second doped region, the second conductive electrode forming a source terminal.

15. The method of claim 9 , further comprising:
forming a third conductive electrode in electrical contact with the first semiconductor layer, the third conductive electrode forming a drain terminal.

16. The method of claim 9 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

17. A normally on high voltage switch device (“normally on switch device”), comprising:
a drain region formed in a first semiconductor layer of a first conductivity type, the first semiconductor layer being heavily doped;
a source region formed on a first surface of a second semiconductor layer of the first conductivity type, the second semiconductor layer being f

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Yilmaz Hamza
• Calafut Daniel
• Padmanabhan Karthik

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title