Semiconductor device including a wall oxide film and method for forming the same

US9530840B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9530840-B2
Application numberUS-201514921831-A
CountryUS
Kind codeB2
Filing dateOct 23, 2015
Priority dateOct 17, 2013
Publication dateDec 27, 2016
Grant dateDec 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor device, the method comprising: forming a first trench defining a line-type partition pattern by etching a semiconductor substrate in a first direction; forming a first wall oxide film having a first thickness over the first trench; forming a first device isolation film over the first wall oxide film by filling the first trench; forming a second trench defining an active region by etching the partition pattern, the first wall oxide film, and the first device isolation film in a second direction crossing the first direction; forming a second wall oxide film having a second thickness over the second trench, the second thickness being different from the first thickness; and forming a second device isolation film over the second wall oxide film by filling the second trench. 2. The method according to claim 1 , wherein the first thickness is greater than the second thickness. 3. The method according to claim 1 , wherein forming the second trench further comprises forming a device isolation trench defining an active region in a peripheral region. 4. The method according to claim 3 , wherein forming the second wall oxide film further comprises forming the second wall oxide film over a sidewall of the device isolation trench of the peripheral region. 5. The method according to claim 4 , wherein forming the second device isolation film comprises forming the second device isolation film over the second wall oxide film by filling the device isolation trench of the peripheral region. 6. The method according to claim 5 , before forming the second device isolation film in the device isolation trench of the peripheral region, further comprising: forming a third wall oxide film over the sidewall of the device isolation trench over which the second wall oxide film is formed, the third wall oxide film having a third thickness. 7. The method according to claim 6 , wherein the third thickness is greater than the first thickness.

Assignees

Inventors

Classifications

  • formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • H10W10/014Primary

    using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • Dielectric isolations, e.g. air gaps · CPC title

  • Complementary IGFETs, e.g. CMOS · CPC title

  • Devices controlled by electric currents or voltages · CPC title

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What does patent US9530840B2 cover?
A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W10/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).