Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

Patent metadata

Field	Value
Publication number	US-9530833-B2
Application number	US-201414307078-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Jun 17, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

First claim

What is claimed:

1. A method, comprising:
providing a semiconductor structure comprising a first interlayer dielectric provided over a semiconductor substrate;
forming a first electrode of a first capacitor over said first interlayer dielectric;
depositing a layer of first dielectric material over said first electrode of said first capacitor and said first interlayer dielectric;
depositing a layer of electrically conductive material over said layer of first dielectric material;
forming a second electrode of said first capacitor and a first electrode of a second capacitor from said layer of electrically conductive material; and
after the formation of said second electrode of said first capacitor and said first electrode of said second capacitor, depositing a layer of second dielectric material and forming a second electrode of said second capacitor over said layer of second dielectric material.

2. The method of claim 1 , wherein said first dielectric material and said second dielectric material differ with respect to their ferroelectric properties.

3. The method of claim 2 , wherein said first dielectric material is substantially non-ferroelectric and said second dielectric material is ferroelectric.

4. The method of claim 3 , wherein said second dielectric material comprises at least one of hafnium dioxide, zirconium dioxide and hafnium zirconium dioxide.

5. The method of claim 4 , further comprising:
after the formation of said second electrode of said second capacitor, depositing a second interlayer dielectric;
planarizing said second interlayer dielectric;
forming a plurality of contact vias in said first interlayer dielectric and said second interlayer dielectric; and
filling said plurality of contact vias with an electrically conductive material, said plurality of contact vias filled with said electrically conductive material providing respective electrical connections to each of said first electrode of said first capacitor, said second electrode of said first capacitor, said first electrode of said second capacitor and said second electrode of said second capacitor.

6. The method of claim 5 , wherein said semiconductor structure further comprises a transistor, one of said contact vias providing electrical connections to said first electrode of said second capacitor and said second electrode of said second capacitor being electrically connected to said transistor, said transistor and said second capacitor forming a nonvolatile memory cell.

7. The method of claim 6 , wherein at least one of said first electrode of said first capacitor, said layer of electrically conductive material and said second electrode of said second capacitor comprises at least one of titanium nitride, tantalum nitride, tantalum and ruthenium.

8. The method of claim 7 , wherein said layer of first dielectric material comprises a material having a greater dielectric constant than silicon dioxide.

9. The method of claim 7 , wherein the deposition of said layer of first dielectric material comprises depositing a first sub-layer of said first electrode of said first capacitor and said first interlayer dielectric, depositing a second sub-layer on said first sub-layer and depositing a third sub-layer on said second sub-layer, wherein each of said first sub-layer and said third sub-layer comprises at least one of hafnium dioxide and zirconium dioxide and said second sub-layer comprises aluminum oxide.

10. The method of claim 1 , further comprising forming a trench in said first interlayer dielectric, wherein at least portions of said layer of electrically conductive material, said second dielectric material and said second electrode of said second capacitor are provided in said trench.

11. The method of claim 10 , wherein the formation of said second electrode of said second capacitor comprises:
depositing a layer of a material of said second electrode on said second capacitor; and
performing a polishing process, said polishing process removing portions of said layer of said material of said second electrode of said second capacitor outside said trench.

12. A method, comprising:
providing a semiconductor structure comprising a first interlayer dielectric provided over a semiconductor substrate;
forming a first electrode of a first capacitor over said first interlayer dielectric;
depositing a layer of substantially non-ferroelectric dielectric material over said first electrode of said first capacitor and said first interlayer dielectric;
depositing a layer of electrically conductive material over said layer of substantially non-ferroelectric dielectric material;
forming a second electrode of said first capacitor and a first electrode of a second capacitor from said layer of electrically conductive material;
depositing a layer of ferroelectric dielectric material above said first and second electrodes; and
forming a second electrode of said second capacitor over said layer of ferroelectric dielectric material.

13. The method of claim 12 , wherein said layer of ferroelectric dielectric material comprises at least one of hafnium dioxide, zirconium dioxide and hafnium zirconium dioxide.

14. The method of claim 12 , further comprising:
depositing a second interlayer dielectric above said first and second capacitors;
planarizing said second interlayer dielectric;
forming a plurality of contact vias in said first interlayer dielectric and said second interlayer dielectric; and
filling said plurality of contact vias with an electrically conductive material, said plurality of contact vias filled with said electrically conductive material providing respective electrical connections to each of said first electrode of said first capacitor, said second electrode of said first capacitor, said first electrode of said second capacitor and said second electrode of said second capacitor.

15. The method of claim 14 , wherein said semiconductor structure further comprises a transistor, one of said contact vias providing electrical connections to said first electrode of said second capacitor and said second electrode of said second capacitor being electrically connected to said transistor, said transistor and said second capacitor forming a nonvolatile memory cell.

16. The method of claim 15 , wherein at least one of said first electrode of said first capacitor, said layer of electrically conductive material and said second electrode of said second capacitor comprises at least one of titanium nitride, tantalum nitride, tantalum and ruthenium.

17. The method of claim 12 , wherein said layer of substantially non-ferroelectric dielectric material comprises a material having a greater dielectric constant than silicon dioxide.

18. The method of claim 15 , wherein depositing said layer of substantially non-ferroelectric dielectric material comprises depositing a first sub-layer on said first electrode of said first capacitor and said layer of substantially non-ferroelectric dielectric material, depositing a second sub-layer on said first sub-layer and depositing a third sub-layer on said second sub-layer, wherein each of said first sub-layer and said third sub-layer comprises at least one of hafnium dioxide and zirconium dioxide and said second sub-layer comprises aluminum oxide.

19. The method of claim 12 , further comprising forming a trench in said first interlayer dielectric, wherein at least portions of said layer of electrically conductive material, said layer of ferroelectric dielectric material and said second electrode of said second capacitor are provided in sai

Assignees

• Globalfoundries Inc
• Globalfoundaries Inc

Inventors

• Triyoso Dina H
• Chu Sanford
• Mueller Johannes
• Polakowski Patrick

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10D84/212

  of only capacitors · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title