Display circuitry with improved transmittance and reduced coupling capacitance

Patent metadata

Field	Value
Publication number	US-9530801-B2
Application number	US-201414153954-A
Country	US
Kind code	B2
Filing date	Jan 13, 2014
Priority date	Jan 13, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. A first low-k dielectric layer may be formed on the passivation layer. Data line routing structures may be formed on the first low-k dielectric layer. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. The first and second low-k dielectric layers may be formed from material having substantially similar refractive indices to maximize backlight transmittance and may have appropriate thicknesses so as to minimize parasitic capacitive loading.

First claim

What is claimed is:

1. Display pixel circuitry, comprising:
a substrate;
a thin-film transistor formed on the substrate, wherein the thin-film transistor has a source terminal, a drain terminal, and a gate conductor that is formed between the source and drain terminals;
a first dielectric layer formed over the thin-film transistor;
a second dielectric layer formed on the first dielectric layer, wherein the first and second dielectric layers have indices of refraction that are within ten percent of each other;
a pixel electrode that makes contact with the drain terminal of the thin-film transistor at a location positioned directly above the gate conductor of the thin-film transistor, wherein the pixel electrode is formed from a conductive material; and
a common electrode that is formed from the conductive material.

2. The display pixel circuitry defined in claim 1 , wherein the first and second dielectric layers are formed from identical dielectric material.

3. The display pixel circuitry defined in claim 1 , wherein the first and second dielectric layers are formed from different dielectric materials having dielectric constants less than that of silicon dioxide.

4. The display pixel circuitry defined in claim 1 , wherein the first dielectric layer is formed from low-k dielectric material.

5. The display pixel circuitry defined in claim 4 , wherein the second dielectric layer is formed from low-k dielectric material.

6. The display pixel circuitry defined in claim 1 , wherein the first dielectric layer comprises photoresist.

7. The display pixel circuitry defined in claim 1 , further comprising:
a passivation layer interposed between the thin-film transistor structures and the first dielectric layer.

8. The display pixel circuitry defined in claim 1 , wherein the common electrode is formed on the second dielectric layer, wherein the pixel electrode is formed at least partially over the common electrode, and wherein the common electrode and a portion of the pixel electrode that is partially formed over the common electrode serve as a storage capacitor for the display pixel circuitry.

9. A method of manufacturing display pixel circuitry, comprising:
forming a top-gate thin-film transistor on a substrate, wherein the thin-film transistor includes a gate conductor and a source-drain region;
forming a first low-k dielectric layer on a passivation layer;
forming a second low-k dielectric layer on the first low-k dielectric layer;
forming a first via through the first low-k dielectric layer, wherein the first via makes contact with the source-drain region of the thin-film transistor;
forming a common electrode using a transparent material; and
forming a second via through the second low-k dielectric layer, wherein the second via contacts the first via at a location directly over the gate conductor of the thin-film transistor.

10. The method defined in claim 9 , wherein the first low-k dielectric layer has a dielectric constant less than that of silicon dioxide.

11. The method defined in claim 9 , wherein the first low-k dielectric layer and the second low-k dielectric layer have refractive indices that are within ten percent of each other.

12. The method defined in claim 11 , further comprising:
forming a storage capacitor for the display pixel circuitry on the second low-k dielectric layer.

13. The method defined in claim 9 , further comprising:
forming a passivation layer directly on the gate conductor of the thin-film transistor.

14. Display pixel structures, comprising:
a substrate;
a thin-film transistor formed over the substrate, wherein the thin-film transistor includes a first source-drain terminal, and a second source-drain terminal, and a gate terminal formed between the first and second source-drain terminals;
a first low-k dielectric layer formed over the thin-film transistor;
a second low-k dielectric layer formed on the first low-k dielectric layer; and
a storage capacitor formed from a pixel electrode and a common electrode, wherein the pixel electrode makes contact with the first source-drain terminal at a pixel contact location positioned directly over the gate terminal of the thin-film transistor, wherein the pixel electrode is formed through the second low-k dielectric layer, and wherein the common electrode and the thin-film transistor are non-overlapping when viewed from above.

15. The display pixel structures defined in claim 14 , further comprising:
a first low-k dielectric layer formed over the thin-film transistor; and
data line routing structures that are formed on the first low-k dielectric layer and that are coupled to the second source-drain terminal.

16. The display pixel structures defined in claim 15 , further comprising:
a second low-k dielectric layer formed on the first low-k dielectric layer, wherein the first and second low-k dielectric layers exhibit substantially similar indices of refraction that differ by less than 0.05.

17. The display pixel structures defined in claim 16 , wherein the first and second low-k dielectric layers are formed from light-sensitive photoresist material and etch resistant material.

18. The display pixel structures defined in claim 15 , further comprising:
a passivation layer interposed between the first low-k dielectric layer and the gate terminal of the thin-film transistor.

Assignees

• Apple Inc

Inventors

• Nozu Daisuke
• Yamagata Hirokazu
• Osawa Hiroshi
• Lin Shang-Chih
• Chang Shih-Chang
• Chen Yu-Cheng

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title