Polysilicon thin film transistor and manufacturing method thereof, array substrate

Patent metadata

Field	Value
Publication number	US-9530799-B2
Application number	US-201314345344-A
Country	US
Kind code	B2
Filing date	Nov 11, 2013
Priority date	Mar 5, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

First claim

The invention claimed is:

1. A manufacturing method of a polysilicon thin film transistor, comprising:
forming a gate electrode, a source electrode, a drain electrode and an active layer on a substrate, wherein the active layer comprises at least a channel area, first patterns located on two sides of the channel area, second patterns located on sides of the first patterns away from the channel area, and third patterns located on the sides of the second patterns away from the first patterns;
forming heavily doped regions at the location of the third patterns, passivated doped regions or lightly doped regions at the location of the second patterns, and the lightly doped regions or the passivated doped regions at the location of the first patterns, by a doping process;
wherein one of the first patterns and the second patterns is the passivated doped regions and the other of the first patterns and the second patterns is the lightly doped regions respectively; doping ions for passivation that form stable covalent bonds with silicon atoms are included in the passivated doped regions, and an implantation depth of the doping ions for passivation in the passivated doped regions is smaller than an implantation depth of ions in the heavily doped regions and the lightly doped regions, and a dosage of the doping ions for passivation in the passivated doped regions is greater than a dosage of ions in the heavily doped regions.

2. The method claimed as claim 1 , wherein the doping process is an ion implantation process.

3. The method claimed as claim 1 , wherein forming of the gate electrode, the source electrode, the drain electrode and the active layer on a substrate as well as the heavily doped regions, the passivated doped regions and the lightly doped regions comprises:
step 1, forming the active layer on the substrate;
step 2, forming a gate insulating layer on the basis of the forgoing step, and forming a first photoresist pattern exactly corresponding to the channel area and the first patterns, the second patterns on the gate insulating layer;
step 3, through one ion implantation process, forming the heavily doped regions at the location of the third patterns;
step 4, after a first layer of photoresist at the location of the first photoresist pattern is removed, forming a metal layer and a second layer of photoresist on the substrate in sequence, after exposure and development are conducted on the second layer of photoresist and the metal layer is etched to form the gate electrode and a second photoresist pattern that is located on the gate electrode and exactly corresponds to the channel area and the first patterns;
step 5, through one ion implantation process, forming the passivated doped regions or the lightly doped regions at the location of the second patterns;
step 6, after the photoresist at the location of the second photoresist pattern is removed, through one ion implantation process, forming the lightly doped regions or the passivated doped regions at the location of the first patterns; and
step 7, after the forgoing steps are completed and an annealing treatment is performed, forming the source electrode and the drain electrode on the substrate.

4. The method claimed as claim 1 , wherein forming the passivated doped regions or the lightly doped regions at the location of the second patterns comprises: forming the passivated doped regions at the location of the second patterns;
forming the lightly doped regions or the passivated doped regions at the location of the first patterns comprises: forming the lightly doped regions at the location of the first patterns.

5. The method claimed as claim 1 , wherein the heavily doped regions are of P type or of N type.

6. The method claimed as claim 1 , wherein forming the active layer on the substrate comprises:
forming a polysilicon layer on the substrate, and by one patterning process treatment, forming the channel area, the first patterns located on two sides of the channel areas, the second patterns located on the sides of the first patterns away from the channel area, and the third patterns located on the sides of the second patterns away from the first patterns.

7. The method claimed as claim 3 , wherein forming the passivated doped regions or the lightly doped regions at the location of the second patterns comprises: forming the passivated doped regions at the location of the second patterns;
forming the lightly doped regions or the passivated doped regions at the location of the first patterns comprises: forming the lightly doped regions at the location of the first patterns.

8. The method claimed as claim 3 , wherein the heavily doped regions are of P type or of N type.

9. The method claimed as claim 3 , wherein forming the active layer on the substrate comprises:
forming a polysilicon layer on the substrate, and by one patterning process treatment, forming the channel area, the first patterns located on two sides of the channel areas, the second patterns located on the sides of the first patterns away from the channel area, and the third patterns located on the sides of the second patterns away from the first patterns.

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Zuqiang

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title