Methods for cell boundary encroachment and semiconductor devices implementing the same

Patent metadata

Field	Value
Publication number	US-9530795-B2
Application number	US-201615051532-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Oct 13, 2009
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor device includes a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first cell including circuitry for performing one or more logic functions, the circuitry of the first cell including a plurality of conductive features defined in one or more levels of the first cell, the first cell having an outer cell boundary defined to circumscribe the first cell, the first cell including a conductive structure formed to extend to within at least one-half of a design rule spacing distance from the outer cell boundary of the first cell at a first location; and
a second cell including circuitry for performing one or more logic functions, the circuitry of the second cell including a plurality of conductive features defined in one or more levels of the second cell, the second cell having an outer cell boundary defined to circumscribe the second cell, a portion of the outer cell boundary of the second cell aligned with a portion of the outer cell boundary of the first cell that includes the first location, the second cell formed to provide a spacing allowance region for the conductive structure of the first cell at the first location.

2. The semiconductor device as recited in claim 1 , wherein the conductive structure of the first cell is linear-shaped having a length extending in a first direction perpendicular to the outer cell boundary of the first cell that includes the first location.

3. The semiconductor device as recited in claim 2 , wherein an end of the conductive structure of the first cell closest to the first location is positioned inside of the first cell.

4. The semiconductor device as recited in claim 2 , wherein an end of the conductive structure of the first cell closest to the first location is positioned outside of the first cell and within the second cell.

5. The semiconductor device as recited in claim 1 , wherein the conductive structure of the first cell includes both a first portion that is parallel to the outer cell boundary of the first cell that includes the first location and a second portion that is perpendicular to the outer cell boundary of the first cell that includes the first location.

6. The semiconductor device as recited in claim 5 , wherein the first portion of the conductive structure of the first cell is positioned inside of the first cell.

7. The semiconductor device as recited in claim 5 , wherein the first portion of the conductive structure of the first cell is positioned inside of both the first cell and the second cell.

8. The semiconductor device as recited in claim 5 , wherein the first portion of the conductive structure of the first cell is positioned inside of the second cell.

9. The semiconductor device as recited in claim 1 , wherein the design rule distance is a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

10. The semiconductor device as recited in claim 9 , wherein the design rule distance is within a range extending from about 30 nanometers to about 90 nanometers.

11. The semiconductor device as recited in claim 9 , wherein the design rule distance is less than 70 nanometers.

12. The semiconductor device as recited in claim 1 , wherein the conductive structure of the first cell is formed within a gate electrode level of the first cell.

13. The semiconductor device as recited in claim 12 , wherein the gate electrode level of the first cell is defined to include only linear-shaped conductive structures positioned parallel to each other.

14. The semiconductor device as recited in claim 1 , wherein the conductive structure of the first cell is a conductive interconnect structure within an interconnect level of the first cell, wherein the interconnect level of the first cell is defined above a gate electrode level of the first cell.

15. The semiconductor device as recited in claim 14 , wherein the interconnect level of the first cell is defined to include only linear-shaped conductive structures positioned parallel to each other.

16. The semiconductor device as recited in claim 1 , wherein the spacing allowance region provided by the second cell at the first location is sized to ensure that a design rule spacing distance exists between the conductive structure of the first cell and any conductive structure in the second cell positioned adjacent to the conductive structure of the first cell.

17. The semiconductor device as recited in claim 1 , wherein a second end of the conductive structure of the first cell is positioned to provide a spacing allowance region at the outer cell boundary of the first cell at a second location across the first cell from the first location.

18. The semiconductor device as recited in claim 1 , wherein a second end of the conductive structure is positioned within at least one-half of a design rule spacing distance from the outer cell boundary of the first cell at a second location across the first cell from the first location.

19. The semiconductor device as recited in claim 18 , wherein the second cell is formed to provide another spacing allowance region at a second location across the second cell from the first location.

20. A method for manufacturing a semiconductor device, comprising:
forming a first cell including circuitry for performing one or more logic functions, the circuitry of the first cell including a plurality of conductive features defined in one or more levels of the first cell, the first cell having an outer cell boundary defined to circumscribe the first cell, the first cell including a conductive structure formed to extend to within at least one-half of a design rule spacing distance from the outer cell boundary of the first cell at a first location; and
forming a second cell including circuitry for performing one or more logic functions, the circuitry of the second cell including a plurality of conductive features defined in one or more levels of the second cell, the second cell having an outer cell boundary defined to circumscribe the second cell, a portion of the outer cell boundary of the second cell aligned with a portion of the outer cell boundary of the first cell that includes the first location, the second cell formed to provide a spacing allowance region for the conductive structure of the first cell at the first location.

Assignees

• Tela Innovations Inc

Inventors

• Quandt Jonathan R
• Becker Scott T
• Gandhi Dhrumil

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title