Systems and methods for integrating bootstrap circuit elements in power transistors and other devices

Patent metadata

Field	Value
Publication number	US-9530773-B2
Application number	US-201514918034-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Dec 18, 2012
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.

First claim

What is claimed is:

1. An integrated circuit comprising:
a floating driver circuit, the floating driver circuit comprising a high side portion, a low side portion, at least one transistor device, and a bootstrap circuit, wherein the bootstrap circuit is integrated on a same die with one of the high side portion or the low side portion and coupled with the at least one transistor device, and wherein, the bootstrap circuit comprises a semiconductor-based bootstrap capacitor device.

2. The integrated circuit of claim 1 , wherein the at least one transistor device comprises a power transistor device.

3. The integrated circuit of claim 1 , wherein the at least one transistor device comprises one of a metal-oxide-semiconductor field effect transistor (MOSFET) device.

4. The integrated circuit of claim 1 , wherein the at least one transistor device comprises a first transistor that is part of the high side portion, the integrated circuit further comprising a second transistor, coupled to the bootstrap circuit, that is part of the low side portion, and wherein the high side portion and the low side portion are integrated on different die of the integrated circuit.

5. The integrated circuit of claim 1 , wherein the at least one transistor device comprises at least one of gallium nitride (GaN) or silicon carbide (SiC).

6. The integrated circuit of claim 1 , wherein the bootstrap circuit is monolithically formed with the at least one transistor device.

7. The integrated circuit of claim 1 , wherein the bootstrap capacitor device comprises a trench formed in a silicon substrate, and wherein a first electrode of the bootstrap capacitor device comprises the silicon substrate and a second electrode of the bootstrap capacitor device comprises a conductive material within and separated from the trench by a dielectric layer.

8. The integrated circuit of claim 1 , wherein the bootstrap capacitor device comprises a trench formed in a silicon substrate, and wherein a doped well surrounds the trench and forms a first electrode of the bootstrap capacitor device, and a second electrode of the bootstrap capacitor device comprises a conductive material within and separated from the trench by a dielectric layer.

9. The integrated circuit of claim 1 , wherein the bootstrap circuit comprises one of a bootstrap diode device or a bootstrap transistor device.

10. The integrated circuit of claim 9 , wherein the bootstrap circuit comprises the bootstrap transistor device, and wherein the bootstrap transistor device comprises a MOSFET device.

11. The integrated circuit of claim 9 , wherein the bootstrap circuit comprises the bootstrap diode device, and wherein the bootstrap diode device comprises a Schottky diode device.

12. A method comprising:
forming at least one transistor device within a floating driver circuit;
forming a high side portion within the floating driver circuit;
forming a low side portion within the floating driver circuit; and
forming a semiconductor-based bootstrap capacitor element within the floating driver circuit, wherein forming the bootstrap capacitor comprises integrating the bootstrap capacitor element on a same die with one of the high side portion or the low side portion and coupling the bootstrap capacitor with the at least one transistor device.

13. The method of claim 12 , wherein forming at least one transistor device comprises forming at least one power transistor device.

14. The method of claim 13 , wherein the at least one power transistor device comprises at least one of a metal-oxide-silicon field effect transistor (MOSFET) device, a silicon carbide (SiC) transistor device or a gallium nitride (GaN) transistor device.

15. The method of claim 14 , wherein forming the semiconductor-based bootstrap capacitor element comprises:
forming a well of the bootstrap capacitor as part of a process of forming the MOSFET device by driving a doping of a first type through a dielectric layer and into a silicon substrate having a doping of a second type different from the first type.

16. The method of claim 15 , further comprising removing the dielectric layer.

17. The method of claim 12 , wherein forming a semiconductor-based bootstrap capacitor element further comprises forming at least one of a bootstrap transistor or a bootstrap diode monolithically with the at least one transistor device.

18. The method of claim 12 , wherein forming a semiconductor-based bootstrap capacitor element further comprises etching at least one trench in a silicon substrate, and wherein forming at least one transistor device further comprises etching at least one trench in the silicon substrate, wherein the at least one trench of the bootstrap capacitor element and the at least one trench of the at least one transistor device are etched to different depths of the silicon substrate.

19. The method of claim 18 , further comprising using the same hardmask to etch the at least one trench of the bootstrap capacitor element and the at least one trench of the at least one transistor device.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Vielemeyer Martin
• Leomant Sylvain
• Paolucci Milko
• Poelzl Martin

Classifications

• H10P32/17

  characterised by the semiconductor material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title