Integrated circuit packaging system with chip stacking and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9530753-B2
Application number	US-201113243474-A
Country	US
Kind code	B2
Filing date	Sep 23, 2011
Priority date	Sep 23, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate.

First claim

What is claimed is:

1. A method of manufacture of an integrated circuit packaging system comprising:
providing a first substrate having a first substrate non-horizontal side;
mounting an integrated circuit structure on the first substrate including:
mounting a base integrated circuit on the first substrate,
attaching an adhesive layer directly on the base integrated circuit, and
mounting a stack device directly on the adhesive layer;

mounting a second substrate on the integrated circuit structure, the second substrate includes conductive layers and conductive traces embedded within the second substrate;
coupling a vertical chip to the first substrate and to the second substrate, the vertical chip having a bond pad, a vertical chip stacking side, and a vertical chip outer side, the vertical chip outer side facing away from the bond pad and perpendicular to the vertical chip stacking side directly on a component side of the first substrate, the bond pad coupled to the first substrate and the second substrate with an arch interconnect, the arch interconnect in direct contact with the bond pad and a top side of the second substrate;
coupling a second vertical chip on the component side and attached to the second substrate, the second vertical chip positioned on the opposite side of the integrated circuit structure; and
forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate, the package body having a cavity between the vertical chip and the second vertical chip, the package body directly on the vertical chip outer side and having a package body outer sidewall coplanar with the first substrate non-horizontal side.

2. The method as claimed in claim 1 wherein coupling the vertical chip includes coupling the vertical chip with a portion of the vertical chip extending above the second substrate.

3. The method as claimed in claim 1 wherein coupling the vertical chip includes forming the arch interconnect for electrically coupling the bond pad to the first substrate.

4. The method as claimed in claim 1 wherein:
mounting the second substrate includes mounting the second substrate having a second substrate contact; and
coupling the vertical chip includes attaching the vertical chip to the second substrate contact for supporting the second substrate.

5. The method as claimed in claim 1 wherein forming the package body includes forming the cavity in the package body, the cavity exposing a non-periphery portion of the second substrate.

6. A method of manufacture of an integrated circuit packaging system comprising:
providing a first substrate having a component side and a first substrate non-horizontal side;
mounting an integrated circuit structure on the component side including:
mounting a base integrated circuit on the first substrate,
attaching an adhesive layer directly on the base integrated circuit, and
mounting a stack device directly on the adhesive layer;

mounting a second substrate, having a substrate non-horizontal side and a second substrate contact, on the integrated circuit structure, the second substrate includes conductive layers and conductive traces embedded within the second substrate;
coupling a vertical chip on the component side and attached to the second substrate, the vertical chip having a bond pad, a vertical chip stacking side, and a vertical chip outer side, the vertical chip outer side facing away from the bond pad and perpendicular to the vertical chip stacking side directly on the component side of the first substrate, the bond pad coupled to the first substrate and the second substrate with an arch interconnect, the arch interconnect in direct contact with the bond pad and a top side of the second substrate contact;
coupling a second vertical chip on the component side and attached to the second substrate, the second vertical chip positioned on the opposite side of the integrated circuit structure; and
forming a package body for encapsulating the component side, the integrated circuit structure, the vertical chip, and a portion of the second substrate, the package body having a cavity between the vertical chip and the second vertical chip, the package body directly on the vertical chip outer side and having a package body outer sidewall coplanar with the first substrate non-horizontal side.

7. The method as claimed in claim 6 further comprising electrically coupling the second vertical chip to the second substrate contact.

8. The method as claimed in claim 6 wherein coupling the vertical chip includes attaching the vertical chip to the substrate non-horizontal side.

9. The method as claimed in claim 6 wherein mounting the integrated circuit structure includes:
mounting the base integrated circuit on the component side of the first substrate; and
attaching the stack device to the second substrate.

10. The method as claimed in claim 6 wherein mounting the integrated circuit structure includes a second stack device over the stack device.

11. An integrated circuit packaging system comprising:
a first substrate having a first substrate non-horizontal side;
an integrated circuit structure mounted on the first substrate, the integrated circuit structure includes:
a base integrated circuit on the first substrate,
an adhesive layer directly on the base integrated circuit, and
a stack device directly on the adhesive layer;

a second substrate mounted on the integrated circuit structure, the second substrate includes conductive layers and conductive traces embedded within the second substrate;
a vertical chip, having a bond pad, a vertical chip stacking side, and a vertical chip outer side, the vertical chip outer side facing away from the bond pad and perpendicular to the vertical chip stacking side directly on a component side of the first substrate, the bond pad coupled to the first substrate and to the second substrate with an arch interconnect, the arch interconnect in direct contact with the bond pad and a top side of the second substrate;
a second vertical chip on the component side and attached to the second substrate, the second vertical chip positioned on the opposite side of the integrated circuit structure; and
a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate, the package body having a cavity between the vertical chip and the second vertical chip, the package body directly on the vertical chip outer side and having a package body outer sidewall coplanar with the first substrate non-horizontal side.

12. The system as claimed in claim 11 wherein the vertical chip includes a portion of the vertical chip extending above the second substrate.

13. The system as claimed in claim 11 wherein the vertical chip includes the arch interconnect for electrically coupling the bond pad to the first substrate.

14. The system as claimed in claim 11 wherein:
the second substrate includes a second substrate contact; and
the vertical chip is attached to the second substrate contact for supporting the second substrate.

15. The system as claimed in claim 11 wherein the package body includes the cavity exposing a non-periphery portion of the second substrate.

16. The system as claimed in claim 11 wherein:
the integrated circuit structure is mounted on the component side;
the second substrate includes a substrate non-horizontal side and a second substrate contact;
the vertical chip is attached to the component side and the second substrate contact; and
the package body encapsulates the component

Assignees

• Kim Daesup
• Kim Youngjoon
• Choi Daesik
• Stats Chippac Pte Ltd

Inventors

• Kim Daesup
• Kim Youngjoon
• Choi Daesik

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title