Optoelectronic component and method for producing same
US-12176444-B2 · Dec 24, 2024 · US
Method for forming electronic components
US9530752B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9530752-B2 |
| Application number | US-201314076976-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 11, 2013 |
| Priority date | Nov 11, 2013 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
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Abstract
Official abstract text for this publication.
A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant, and forming electrically conductive contacts for electrically contacting the at least partially encapsulated electronic chips.
First claim
Opening claim text (preview).
What is claimed is: 1. A method, the method comprising: arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate; at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant; forming electrically conductive contacts…
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Cross-Sectional Technologies · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W72/0198Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9530752B2 cover?
- A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an e…
- Who is the assignee on this patent?
- Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification H10W72/0198. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).