Flexible electronic circuit and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9530708-B1
Application number	US-201313906750-A
Country	US
Kind code	B1
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

First claim

What is claimed is:

1. An electronic circuit comprising:
an integrated circuit chip, the integrated circuit chip having a top face;

portions of the top face of the chip being covered by a bottom surface of a first metal layer electrically connected to the integrated circuit; and
a dielectric layer formed on the top face of the chip beside and on top of said first metal layer;
wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip;
wherein portions of a top surface of the dielectric layer are covered by a second metal layer formed on and in contact with said dielectric layer, portions of a top surface of the first metal layer being electrically connected through the dielectric layer to portions of a bottom surface of the second metal layer.

2. The electronic circuit of claim 1 , wherein the material and the thickness of the dielectric layer are such that the dielectric layer and the first and second metal layers form a flexible layer that can be rolled or conformed to a shape.

3. The electronic circuit of claim 1 , wherein said integrated circuit chip comprises an active circuit or component formed in a substrate as well as a portion of said substrate limited to around said active circuit or component.

4. The electronic circuit of claim 1 , wherein the integrated circuit chip comprises an integrated circuit formed in a semiconductor epitaxial layer, the epitaxial layer having been formed on a substrate; the first metal layer and the dielectric layer having been formed on the top face of the epitaxial layer; and
wherein the substrate has been etched away from the bottom of the epitaxial layer and the epitaxial layer has been etched away from the bottom of the dielectric layer, except in the vicinity of said integrated circuit.

5. The electronic circuit of claim 1 , comprising a third metal layer on the bottom face of the integrated circuit chip.

6. The electronic circuit of claim 5 , wherein at least a portion of the third metal layer is connected to at least a portion of the first metal layer.

7. The electronic circuit of claim 5 , wherein the integrated circuit chip comprises at least one signal-carrying conductor not electrically connected to the third metal layer; and
wherein the third metal layer is arranged to not overlap said at least one signal-carrying conductor.

8. The electronic circuit of claim 1 , wherein a portion of one of the first and second metal layers forms a signal-carrying conductor having a given shape; and wherein a substantially identically shaped conductor, formed in the other of the one of the first and second metal layers, is connected to the ground.

9. The electronic circuit of claim 1 , wherein the integrated circuit is a high frequency active circuit and wherein a portion of one of the first and second metal layers forms a passive component of a high frequency circuit.

10. A circuit assembly comprising:
a substrate having a surface; electronic passive elements and conductors formed on said substrate surface; and
an electronic circuit of claim 1 attached to said substrate surface such that one of the first and second metal layers is electrically coupled to said conductors formed on said substrate surface.

11. An electronic circuit comprising:
an integrated circuit chip, the integrated circuit chip having a top face;

portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and
a dielectric layer formed on the top face of the chip beside and on top of said first metal layer;
wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip;
wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer,
wherein the material and the thickness of the dielectric layer are such that the dielectric layer and the first and second metal layers form a flexible layer that can be rolled or conformed to a shape.

Assignees

• Hrl Lab Llc

Inventors

• Sharifi Hasan
• Shinohara Keisuke
• Montes Mary C
• Mcguire Charles
• Ha Wonill
• May Jason
• Kazemi Hooman
• Kang Jongchan
• Nagele Robert G

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/07337

  using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title