Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9530696-B1
Application number	US-201514921514-A
Country	US
Kind code	B1
Filing date	Oct 23, 2015
Priority date	Oct 23, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder on a substrate;
before forming the plurality of sacrificial gates and the plurality of sacrificial gate dielectric layers, patterning the substrate to form a plurality of fins, wherein the plurality sacrificial gate dielectric layers are disposed on the plurality of fins;
filling an interlayer dielectric layer between the sacrificial gates;
forming a protective layer on the interlayer dielectric layer;
removing the sacrificial gates and the sacrificial gate dielectric layers to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing; and
forming a stacked gate structure in the opening, wherein the protective layer is removed.

2. The method of fabricating the semiconductor device according to claim 1 , wherein a method of forming the protective layer comprises a combination of a deposition process, a lithography process, and an etching process.

3. The method of fabricating the semiconductor device according to claim 1 , wherein a material of the protective layer comprises metal oxide, metal nitride, SiN, SiCN, SiC or SiON.

4. The method of fabricating the semiconductor device according to claim 1 , wherein the sacrificial gate dielectric layer comprises a first silicon oxide, and the interlayer dielectric layer comprises a second silicon oxide.

5. The method of fabricating the semiconductor device according to claim 1 , wherein forming the sacrificial gate dielectric layer and forming a gate dielectric layer of an I/O device area are at the same time, and forming the sacrificial gate and forming a gate of the I/O device area are at the same time.

6. The method of fabricating the semiconductor device according to claim 1 , wherein the stacked gate structure comprises a gate dielectric layer and a metal gate layer, and the metal gate layer is disposed on the gate dielectric layer.

7. The method of fabricating the semiconductor device according to claim 6 , wherein a method of forming the stacked gate structure and removing the protective layer comprising:
forming a gate dielectric material layer and a metal gate material layer sequentially; and
performing a chemical mechanical polishing process to remove the gate dielectric material layer and the metal gate material layer outside the opening and to remove the protective layer.

8. The method of fabricating the semiconductor device according to claim 6 , wherein the metal gate layer comprises a work function metal layer and a low resistance metal layer formed sequentially.

9. The method of fabricating the semiconductor device according to claim 1 , after forming the sacrificial gates and before filling the interlayer dielectric layer, further comprising:
forming spacers on sidewalls of the sacrificial gates;
removing parts of the substrate between the spacers, and
growing an epitaxial layer from the substrate between the spacers, wherein the epitaxial layer has different lattice constant from the substrate.

10. The method of fabricating the semiconductor device according to claim 9 , wherein a material of the epitaxial layer comprises SiGe or SiP.

11. The method of fabricating the semiconductor device according to claim 9 , after forming the epitaxial layer, further comprising forming a contact etch stop layer on the spacers and the epitaxial layer.

Assignees

• United Microelectronics Corp

Inventors

• Liu Wei-Hsin
• Tsai Fu-Yu
• Tsai Bin-Siang
• Hsu Wei-Lun
• Yang Shang-Yi
• Lai Pi-Hsuan

Classifications

• H10D84/0133

  Manufacturing common source or drain regions between multiple IGFETs · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title