Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9530693-B2
Application number	US-201514677903-A
Country	US
Kind code	B2
Filing date	Apr 2, 2015
Priority date	Jul 12, 2012
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a dummy active region, a first active region, and a second active region defined by an isolation layer in a semiconductor substrate, wherein the dummy active region is disposed between the first active region and the second active region;
implanting a first type of impurity ions into the dummy active region; and
implanting a second type of impurity ions into the first active region and the first type of impurity ions into the second active region,
wherein a concentration of impurity ions of the dummy active region is higher than a concentration of impurity ions of the second active region.

2. The method of claim 1 , wherein implanting impurity ions into the first and second active regions includes:
implanting N type impurity ions into the first active region to form a N type well; and
implanting P type impurity ions into the second active region to form a P type well.

3. The method of claim 2 , further comprising:
implanting N type impurity ions in the N type well to form an N+ type junction region; and
implanting P type impurity ions into the P type well to form a P+ type junction region.

4. The method of claim 1 , wherein implanting the impurity ions into the dummy active region includes implanting an N type impurity or a P type impurity into the dummy active region.

5. The semiconductor device of claim 1 , wherein the dummy active region is formed in a peripheral region.

6. The method of claim 1 , further comprising sequentially stacking a polysilicon layer, a conductive layer, a hard mask layer on at least one of the isolation layer, the dummy active region, the first active region, and the second active region and patterning the layers to form a gate structure.

7. The method of claim 6 , further comprising:
depositing an interlayer insulating layer on the semiconductor substrate including the gate structure;
etching the interlayer insulating layer on any one of the first and second active regions to form a bit line contact hole; and
depositing a conductive material in the bit line contact hole.

8. The method of claim 1 , further comprising forming a through silicon via (TSV) around the dummy active region, the first active region, or the second active region.

9. The method of claim 8 , wherein P type impurity ions are implanted in the dummy active region.

10. The method of claim 1 , wherein the first concentration is at least 1.2 times greater than the second concentration.

11. The method of claim 8 , wherein the dummy active region is formed between the through silicon via (TSV) and the second active region.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jong Il

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P36/03

  within silicon bodies · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/01308

  the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal · CPC title