MOS transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9530686-B1
Application number	US-201615043830-A
Country	US
Kind code	B1
Filing date	Feb 15, 2016
Priority date	Aug 24, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

First claim

The invention claimed is:

1. A method of manufacturing a MOS transistor, comprising the steps of:
a) forming insulating walls penetrating into a semiconductor substrate coated with a first insulating layer and with a first semiconductor layer, said insulating walls laterally delimiting a location of the MOS transistor;
b) forming a gate stack coated with a second insulating layer on the first semiconductor layer;
c) etching, between the insulating walls and on each side of the gate stack, the first semiconductor layer and the first insulating layer all the way to the semiconductor substrate to form openings;
d) epitaxially growing in said openings a sacrificial semiconductor layer from the semiconductor substrate to an intermediate level of the first insulating layer;
e) epitaxially growing a second semiconductor layer from the sacrificial semiconductor layer to an upper level of the first semiconductor layer;
f) etching the insulating walls to laterally expose the sacrificial semiconductor layer;
g) removing the sacrificial semiconductor layer to form cavities between the semiconductor substrate and the second semiconductor layer; and
h) filling said cavities with at least one insulator.

2. The method of claim 1 , wherein the semiconductor substrate and the second semiconductor layer are made of silicon, and the sacrificial semiconductor layer is made of silicon-germanium.

3. The method of claim 1 , further comprising, between steps f) and g):
forming a third insulating layer on walls of the cavities, on the gate stack and on exposed surfaces of the second semiconductor layer; and
removing the portions of the third insulating layer resting on the upper surface of the second semiconductor layer and on the top of the gate stack.

4. The method of claim 3 , wherein the third insulating layer is made of silicon oxide.

5. The method of claim 1 , wherein step h) comprises:
depositing a fourth insulating layer on the gate stack, the second semiconductor layer and in the cavities, and
then removing the portions of the fourth insulating layer resting on the top of the gate stack and on the upper surface of the second semiconductor layer to form spacers on either side of the gate stack.

6. The method of claim 5 , wherein the fourth insulating layer is made of silicon nitride.

7. The method of claim 1 , further comprising, after step h), removing a portion of the second insulating layer resting on the top of the gate stack by etching to form spacers on either side of the gate stack.

8. The method of claim 2 , wherein the second insulating layer is made of silicon nitride.

9. The method of claim 1 , wherein a thickness of the second semiconductor layer is between 8 nm and 75 nm.

10. The method of claim 1 , wherein a thickness of the first semiconductor layer is between 3 nm and 30 nm.

11. A method, comprising:
forming a gate stack on top of a silicon on insulator substrate having a semiconductor substrate coated with a first insulating layer and with a first semiconductor layer;
using the gate stack as a mask to etch the silicon on insulator substrate to remove the first insulating layer and first semiconductor layer forming openings on each side of the gate stack;
epitaxially growing a sacrificial semiconductor layer from the semiconductor substrate at a bottom of each opening;
epitaxially growing a second semiconductor layer from the sacrificial semiconductor layer in each opening to form source and drain regions on opposite sides of a channel region formed by a portion of the first semiconductor layer under the gate stack;
removing the sacrificial semiconductor layer to form cavities under the source and drain regions; and
filling the cavities with an insulating material.

12. The method of claim 11 , wherein filling comprises depositing an insulating liner that lines the bottom of the source and drain regions, a side of a portion of the first insulating layer under the gate stack and an upper surface of the semiconductor substrate.

13. The method of claim 12 , wherein depositing the insulating liner further comprises depositing the insulating liner on sidewalls of the gate stack.

14. The method of claim 12 , wherein filling further comprises depositing an insulating fill material in contact with the insulating liner.

15. The method of claim 12 ,
wherein depositing the insulating liner further comprises depositing the insulating liner on sidewalls of the gate stack; and
wherein depositing the insulating fill material further comprises depositing the insulating fill material on sidewalls of the gate stack.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Bidal Gregory

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01304

  characterised by the conductor · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title