Array structure of single-ploy nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9530460-B2
Application number	US-201615151013-A
Country	US
Kind code	B2
Filing date	May 10, 2016
Priority date	Apr 2, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

First claim

What is claimed is:

1. An array structure of a single-poly nonvolatile memory, the array structure comprising:
a first MTP section comprising a first row of MTP cells connected to a first word line, a first source line, a first erase line and a plurality of bit lines; and
a second MTP section comprising a second row of MTP cells connected to a second word line, a second source line; wherein the second MTP section shared the first erase line and the plurality of bit lines with the first MTP section; and
a first ROM section comprising a third row of ROM cells connected to a third word line; wherein the first ROM section shared the first source line and the plurality of bit lines with the first MTP section.

2. The array structure as claimed in claim 1 , wherein the plurality of bit lines comprise a first bit line and a second bit line; and the first MTP section comprises a first memory cell comprising a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, wherein a source terminal of the first PMOS transistor is connected to the first source line, a gate terminal of the first PMOS transistor is connected to the first word line, a drain terminal of the first PMOS transistor is connected to a source terminal of the second PMOS transistor, a drain terminal of the second PMOS transistor is connected to the first bit line, a gate terminal of the second PMOS transistor is connected to a gate terminal of the first NMOS transistor, and a drain terminal and a source terminal of the first NMOS transistor are connected to the first erase line; and the first MTP section comprises a second memory cell comprising a third PMOS transistor, a fourth PMOS transistor and a second NMOS transistor, wherein a source terminal of the third PMOS transistor is connected to the first source line, a gate terminal of the third PMOS transistor is connected to the first word line, a drain terminal of the third PMOS transistor is connected to a source terminal of the fourth PMOS transistor, a drain terminal of the fourth PMOS transistor is connected to the second bit line, a gate terminal of the fourth PMOS transistor is connected to a gate terminal of the second NMOS transistor, and a drain terminal and a source terminal of the second NMOS transistor are connected to the first erase line.

3. The array structure as claimed in claim 2 , wherein the second MTP section comprises a third memory cell comprising a fifth PMOS transistor, a sixth PMOS transistor and a third NMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to the second source line, a gate terminal of the fifth PMOS transistor is connected to the second word line, a drain terminal of the fifth PMOS transistor is connected to a source terminal of the sixth PMOS transistor, a drain terminal of the sixth PMOS transistor is connected to the first bit line, a gate terminal of the sixth PMOS transistor is connected to a gate terminal of the third NMOS transistor, and a drain terminal and a source terminal of the third NMOS transistor are connected to the first erase line; and the second MTP section comprises a fourth memory cell comprising a seventh PMOS transistor, an eighth PMOS transistor and a fourth NMOS transistor, wherein a source terminal of the seventh PMOS transistor is connected to the second source line, a gate terminal of the seventh PMOS transistor is connected to the second word line, a drain terminal of the seventh PMOS transistor is connected to a source terminal of the eighth PMOS transistor, a drain terminal of the eighth PMOS transistor is connected to the second bit line, a gate terminal of the eighth PMOS transistor is connected to a gate terminal of the fourth NMOS transistor, and a drain terminal and a source terminal of the fourth NMOS transistor are connected to the first erase line.

4. The array structure as claimed in claim 2 , wherein the first ROM section comprises a third memory cell comprising a fifth PMOS transistor and a sixth PMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to the first source line, a gate terminal of the fifth PMOS transistor is connected to the third word line, a drain terminal of the fifth PMOS transistor is connected to a source terminal of the sixth PMOS transistor, and a drain terminal of the sixth PMOS transistor is connected to the first bit line; and the first ROM section comprises a fourth memory cell comprising a seventh PMOS transistor, wherein a source terminal of the seventh PMOS transistor is connected to the first source line, a gate terminal of the seventh PMOS transistor is connected to the third word line, and a drain terminal of the seventh PMOS transistor is connected to the second bit line.

5. The array structure as claimed in claim 2 , further comprising:
a second ROM section comprising a fourth row of ROM cells connected to a fourth word line, a third source line, wherein the second ROM section shared the plurality of bit lines with the first MTP section.

6. The array structure as claimed in claim 5 , wherein the second ROM section comprises a third memory cell comprising a fifth PMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to the third source line, a gate terminal of the fifth PMOS transistor is connected to the fourth word line, a drain terminal of the fifth PMOS transistor is connected to the first bit line; and the second ROM section comprises a fourth memory cell comprising a sixth PMOS transistor and a seventh PMOS transistor, wherein a source terminal of the sixth PMOS transistor is connected to the third source line, a gate terminal of the sixth PMOS transistor is connected to the fourth word line, and a drain terminal of the sixth PMOS transistor is connected to a source terminal of the seventh PMOS transistor, and a drain terminal of the seventh PMOS transistor is connected to the second bit line.

Assignees

• Ememory Technology Inc

Inventors

• Chen Wei-Ren
• Lee Wen-Hao

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title