Data processing device

Patent metadata

Field	Value
Publication number	US-9530457-B2
Application number	US-201414519967-A
Country	US
Kind code	B2
Filing date	Oct 21, 2014
Priority date	Feb 10, 2006
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a semiconductor board including a surface comprised of a quadrangle in plan view, the surface including a first side, a second side facing the first side, a third side crossing the first and second sides, and a fourth side facing the third side and also crossing the first and second sides;
a plurality of first pads coupling with a first memory interface circuit formed over the surface of the semiconductor board, the first pads being arranged along the first side of the surface of the semiconductor board in plan view, the first pads being arranged closer to the first side of the surface of the semiconductor board than the second side of the surface of the semiconductor board in plan view; and
a plurality of second pads coupling with a second memory interface circuit formed over the surface of the semiconductor board, the second pads being arranged along the third side of the surface of the semiconductor board in plan view, the second pads being arranged closer to the third side of the surface of the semiconductor board than the fourth side of the surface of the semiconductor board in plan view,
wherein the first memory interface circuit has a plurality of first data units coupled to the plurality of first pads,
wherein the second memory interface circuit has a plurality of second data units coupled to the plurality of second pads, and
wherein the plurality of second data units of the second memory interface circuit are the same as the plurality of first data units of the first memory interface circuit.

2. The semiconductor chip according to claim 1 , wherein the first memory interface circuit has a first address unit,
wherein the second memory interface circuit has a second address unit, and
wherein the second address unit of the second memory interface circuit is the same as the first address unit of the first memory interface circuit.

3. The semiconductor chip according to claim 2 ,
wherein in the first memory interface circuit, the first data unit and the first address unit are arranged along the first side of the surface of the semiconductor board in series, and
wherein in the second memory interface circuit, the second data unit and the second address unit are arranged along the third side of the surface of the semiconductor board in series.

4. The semiconductor chip according to claim 1 ,
wherein each of the first memory interface circuit and the second memory interface circuit is connectable with SDRAM of Double Data Rate type, having a pin arrangement in conformity with JEDEC STANDARD.

5. The semiconductor chip according to claim 1 ,
wherein the first pads are arranged closer to a first corner of the first and third sides of the surface of the semiconductor board than a second corner of the first and fourth sides of the surface of the semiconductor board in the plan view; and
wherein the second pads are arranged closer to the first corner of the surface of the semiconductor board than a third corner of the second and third sides of the surface of the semiconductor board in the plan view.

6. A semiconductor device comprising:
a substrate including a first surface, and a second surface opposite to the first surface;
a semiconductor chip mounted over the first surface of the substrate, the semiconductor chip including:
a semiconductor board including a surface comprised of a quadrangle in plan view, the surface having a first side, a second side facing the first side, a third side crossing the first and second sides, and a fourth side facing the third side and also crossing the first and second sides,
a plurality of first pads coupling with a first memory interface circuit formed over the surface of the semiconductor board, the first pads being arranged along the first side of the surface of the semiconductor board in plan view, the first pads being arranged closer to the first side of the surface of the semiconductor board than the second side of the surface of the semiconductor board in plan view, and
a plurality of second pads coupling with a second memory interface circuit formed over the surface of the semiconductor board, the second pads being arranged along the third side of the surface of the semiconductor board in plan view, the second pads being arranged closer to the third side of the surface of the semiconductor board than the fourth side of the surface of the semiconductor board in plan view; and

a plurality of external terminals formed over the second surface of the substrate,
wherein the first memory interface circuit has a plurality of first data units coupled to the plurality of first pads,
wherein the second memory interface circuit has a plurality of second data units coupled to the plurality of second pads, and
wherein the plurality of second data units of the second memory interface circuit are the same as the plurality of first data units of the first memory interface circuit.

Assignees

• Renesas Electronics Corp

Inventors

• Betsui Takafumi
• Taoka Naoto
• Suwa Motoo
• Matsui Shigezumi
• Sugita Norihiko
• Fukushima Yoshiharu

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• H05K3/4602

  characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated · CPC title

• H05K2201/09236

  Parallel layout · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title