System and method for a processing device with a priority interrupt

Patent metadata

Field	Value
Publication number	US-9530008-B2
Application number	US-201313904957-A
Country	US
Kind code	B2
Filing date	May 29, 2013
Priority date	May 29, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal.

First claim

What is claimed is:

1. A method of operating a processor, the method comprising:
operating in a first operating mode that prohibits access to a protected memory area;
receiving a priority interrupt (PI) signal from a first data interface when the first data interface has first data ready to read;
operating in a second operating mode in response to receiving the PI signal, wherein access to the protected memory area is permitted in the second operating mode;
reading the first data from the first data interface;
storing the first data in the protected memory area; and
executing a first routine by asserting a semi-privileged interrupt (SPI) signal, wherein the first routine operates in the second operating mode and is interruptible by the PI signal.

2. The method of claim 1 , wherein:
executing the first routine comprises reading the first data from the protected memory area.

3. The method of claim 1 , wherein:
the PI signal is a non-maskable interrupt (NMI) signal; and
the SPI signal is an interrupt signal one priority lower than the NMI signal.

4. The method of claim 1 , wherein reading the first data from the first data interface comprises reading the first data from an analog-to-digital (A/D) converter.

5. A method of operating a processor, the method comprising:
operating in a first operating mode that prohibits access to a protected memory area;
receiving a priority interrupt (PI) signal;
operating in a second operating mode in response to receiving the PI signal, wherein access to the protected memory area is permitted in the second operating mode;
writing first data into the protected memory area while operating in the second operating mode:
executing a first routine by asserting a semi-privileged interrupt (SPI), wherein the first routine operates in the second operating mode and is interruptible by the PI signal, the first routine comprising:
reading the first data from the protected memory area;
computing an encryption signature on the first data; and
writing the encryption signature to a first interface.

6. The method of claim 5 , wherein writing the encryption signature to the first interface comprises writing the encryption signature to a memory.

7. The method of claim 5 , wherein writing the encryption signature to the first interface comprises writing the encryption signature to a communication interface.

8. The method of claim 5 , wherein:
a PI signal is a non-maskable interrupt (NMI) signal; and
the SPI signal is an interrupt signal of a lower priority than the NMI signal.

9. A system comprising:
a first data interface; and
a processor comprising a priority interrupt (PI) input configured to receive a PI signal from the first data interface when the first data interface has first data ready to read, wherein the processor is configured to
operate in a first operating mode that prohibits access to a protected memory area,
operate in a second operating mode in response to receiving the PI signal, wherein access to the protected memory area is permitted in the second operating mode,
read the first data from the first data interface,
store the first data in the protected memory area, and
execute a first routine by asserting a semi-privileged interrupt (SPI) signal, wherein the first routine operates in the second operating mode and is interruptible by the PI signal.

10. The system of claim 9 , further comprising a control unit coupled to the protected memory area, wherein the control unit is configured to prevent access to the protected memory area when the system operates in the first operating mode.

11. The system of claim 9 , wherein:
the PI signal is a non-maskable interrupt (NMI) signal; and
the SPI signal is an interrupt signal one priority lower than the NMI signal.

12. The system of claim 9 ,
wherein executing the first routine comprises reading the first data from the protected memory area.

13. A system comprising:
a first interface; and
a processor comprising a priority interrupt (PI) input configured to receive a PI signal, wherein the processor is configured to
operate in a first operating mode that prohibits access to a protected memory area,
operate in a second operating mode in response to receiving the PI signal, wherein access to the protected memory area is permitted in the second operating mode,
write first data into the protected memory area while operating in the second operating mode, and
execute a first routine by asserting a semi-privileged interrupt (SPI), wherein the first routine operates in the second operating mode and is interruptible by the PI signal, wherein the first routine is configured to
read the first data from the protected memory area,
compute an encryption signature on the first data, and
write the encryption signature to the first interface.

14. The system of claim 13 , wherein the first interface comprises a memory interface.

15. The system of claim 13 , wherein the first interface comprises a communication interface.

16. A system comprising:
a processor comprising a priority interrupt (PI) input configured to receive a PI signal, wherein the processor is configured to
operate in a first operating mode that prohibits access to a protected memory area,
operate in a second operating mode in response to receiving the PI signal, wherein access to the protected memory area is permitted in the second operating mode,
write first data into the protected memory area while operating in the second operating mode, and
execute a first routine by asserting a semi-privileged interrupt (SPI), wherein the first routine operates in the second operating mode and is interruptible by the PI signal, wherein the first routine is configured to read the first data from the protected memory area; and

an analog-to-digital (A/D) converter configured to provide the first data, and wherein the system is further configured to assert the PI signal when the A/D converter has performed a conversion.

17. A system comprising:
a processor comprising a priority interrupt (PI) input configured to receive a PI signal, wherein the processor is configured to
operate in a first operating mode that prohibits access to a protected memory area,
operate in a second operating mode in response to receiving the PI signal, wherein access to the protected memory area is permitted in the second operating mode,
write first data into the protected memory area while operating in the second operating mode,
execute a first routine by asserting a semi-privileged interrupt (SPI) signal, wherein the first routine operates in the second operating mode and is interruptible by the PI signal, wherein the first routine is configured to read the first data from the protected memory area, and
assert the SPI signal within a first time period after receiving the PI signal for a first percentage of received PI signals.

18. An electronic meter comprising:
an analog front-end (AFE) configured to be coupled to a sensor, wherein the AFE comprises a data output interface and a priority interrupt (PI) signal output;
a processor coupled to the data output interface and the PI signal output of the AFE; and
a memory coupled to the processor, wherein the processor is configured to
operate in a first operating mode that prohibits access to a protected memory area,
operate in a second operating mode in response to the PI signal being asserted by the AFE, wherein access to the protected memory area is permitted in the second operating mode,
write first data to the protected memory area while oper

Assignees

• Infineon Technologies Ag

Inventors

• Helmschmidt Juergen
• Parodi Fabio
• Schoenfeldt Stephan
• Rossi Sergio

Classifications

• G06F21/60 Primary

  Protecting data · CPC title

• G06F21/604

  Tools and structures for managing or administering access control systems · CPC title

• G06F13/26

  with priority control · CPC title

• G06F21/575

  Secure boot · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title