Active region design layout

Patent metadata

Field	Value
Publication number	US-9529956-B2
Application number	US-201414454579-A
Country	US
Kind code	B2
Filing date	Aug 7, 2014
Priority date	Aug 7, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

The integrated circuit (IC) device includes a substrate, an isolation feature, a first gate structure, a second gate structure, a first contact feature and a first supplementary active region. The isolation feature is disposed in the substrate, and the isolation feature defines a boundary between a first active region and a second active region of the substrate. The first gate structure is disposed over the first active region. The second gate structure is disposed over the second active region. The first contact feature is disposed over the first active region, in which a portion of the first active region is disposed between the first gate structure and the isolation feature. The first supplementary active region is disposed adjacent to the portion of the first active region, in which a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm.

First claim

What is claimed is:

1. A method, comprising:
providing a first integrated circuit design layout that includes a first active region, a second active region, a first contact feature, a second contact feature and an isolation feature, wherein a portion of the first active region is disposed between the first contact feature and the isolation feature, and a portion of the second active region is disposed between the second contact feature and the isolation feature;
adding a first supplementary active region adjacent to the portion of the first active region disposed between the first contact feature and the isolation feature to form a second integrated circuit design layout, wherein a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm;
determining whether a first distance between the portion of the second active region and the first supplementary active region is smaller than a threshold value;
removing a portion of the first supplementary active region if the first distance is smaller than the threshold value; and
forming an integrated circuit device by the second integrated circuit design layout.

2. The method of claim 1 , further comprising fabricating a mask according to the second integrated circuit design layout.

3. The method of claim 1 , wherein determining whether the thickness of the portion of the first active region disposed between the first contact feature and the isolation feature is smaller than the threshold value further comprises determining whether the first distance is smaller than a minimum design rule thickness.

4. The method of claim 1 , wherein the threshold value is 80 nm.

5. The method of claim 1 , further comprising:
adding a second supplementary active region adjacent to the portion of the second active region disposed between the second contact feature and the isolation feature, wherein a thickness of the second supplementary active region is substantially in a range from 5 nm to 10 nm;
determining whether a second distance between the second supplementary active region and the first supplementary active region is smaller than the threshold value; and
removing a portion of the second supplementary active region if the second distance is smaller than the threshold value.

6. A method comprising:
providing a first integrated circuit design layout, wherein the first integrated circuit design layout includes:
a first layout including an isolation feature that defines a first active region and a second active region; and
a second layout including a first contact feature and a second contact feature, the first layout and the second layout having a spatial relationship, wherein a portion of the first active region is disposed between the first contact feature and the isolation feature, and a portion of the second active region is disposed between the second contact feature and the isolation feature;

adding a first supplementary active region adjacent to the portion of the first active region disposed between the first contact feature and the isolation feature in the first layout to form an amended layout, and a second integrated circuit design layout including the amended layout and the second layout, wherein a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm;
determining whether a first distance between the portion of the second active region and the first supplementary active region is smaller than a threshold value;
removing a portion of the first supplementary active region if the first distance is smaller than the threshold value; and
forming an integrated circuit device in accordance with the second integrated circuit design layout.

7. The method of claim 6 , further comprising fabricating a first mask according to the amended layout.

8. The method of claim 6 , further comprising fabricating a second mask according to the second layout.

9. The method of claim 6 , wherein determining whether the thickness of the portion of the first active region disposed between the first contact feature and the isolation feature is smaller than the threshold value further comprises determining whether the first distance is smaller than or equal to a minimum design rule thickness.

10. The method of claim 6 , wherein the threshold value is 80 nm.

11. The method of claim 6 , further comprising:
adding a second supplementary active region adjacent to the portion of the second active region disposed between the second contact feature and the isolation feature in the amended layout, wherein a thickness of the second supplementary active region is substantially in a range from 5 nm to 10 nm;
determining whether a second distance between the portion of the second supplementary active region and the first supplementary active region is smaller than the threshold value; and
removing a portion of the second supplementary active region if the second distance is smaller than the threshold value.

12. The method of claim 6 , wherein the second integrated circuit design layout further comprises a third layout including a first gate structure, the amended layout, the second layout, and the third layout having a spatial relationship, wherein the first contact feature is disposed over the first active region between the first gate structure and the isolation feature.

13. The method of claim 12 , wherein the third layout further comprises a second gate structure, wherein the second contact feature is disposed over the second active region between the second gate structure and the isolation feature.

14. The method of claim 13 , further comprising fabricating a third mask according to the third layout.

15. A method for forming an integrated circuit (IC) device, the method comprising:
providing a substrate;
forming an isolation feature in the substrate, the isolation feature defining a boundary between a first active region and a second active region of the substrate;
forming a first gate structure over the first active region;
forming a second gate structure over the second active region;
forming a first contact feature over the first active region, wherein a portion of the first active region is disposed between the first gate structure and the isolation feature;
forming a second contact feature over the second active region, wherein a portion of the second active region is disposed between the second gate structure and the isolation feature;
forming a first supplementary active region adjacent to the portion of the first active region, wherein a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm;
determining whether a first distance between the portion of the second active region and the first supplementary active region is smaller than a threshold value; and
removing a portion of the first supplementary active region if the first distance is smaller than the threshold value.

16. The method of claim 15 , further comprising forming a second supplementary active region adjacent to the portion of the second active region, wherein a thickness of the second supplementary active region is substantially in a range from 5 nm to 10 nm.

17. The method of claim 16 , wherein a second distance between the portion of the first active region and the second supplementary active region is smaller than a threshold value.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Chen-Liang
• Cheng Cheng-Wei
• Lei Ming
• Huang Yi-Lii

Classifications

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00 Primary

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H10D89/10

  Integrated device layouts · CPC title