Integrated circuit (IC) with reconfigurable digital voltage regulator fabric

Patent metadata

Field	Value
Publication number	US-9529765-B2
Application number	US-201414313817-A
Country	US
Kind code	B2
Filing date	Jun 24, 2014
Priority date	Jun 24, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Described is an apparatus which comprises: a plurality of bridges which are operable to drive respective signals for one or more power supply rails; a plurality of controllers; and a main controller to couple one or more controllers from the plurality of controllers to one or more bridges from the plurality of bridges.

First claim

We claim:

1. An integrated circuit comprising:
a plurality of bridges which are operable to drive respective signals for one or more power supply rails;
a plurality of controllers;
a main controller to couple one or more controllers from the plurality of controllers to one or more bridges from the plurality of bridges; and
a non-volatile memory (NVM) coupled to the main controller, the NVM to store a plurality of configurations for coupling the plurality of bridges with the plurality of controllers, the plurality of configurations including one or more of:
switching frequency for each of the plurality of bridges;
compensation filter characteristics for each of the plurality of controllers; or
coupling information for each controller and each bridge of the plurality of controllers and bridges.

2. The integrated circuit of claim 1 further comprises a plurality of analog-to-digital converters (ADCs) for converting voltage levels on the one or more power supply rails to their respective digital representations.

3. The integrated circuit of claim 2 , wherein the plurality of ADCs is coupled to the plurality of controllers.

4. The integrated circuit of claim 2 , wherein each of the plurality of controllers includes a digital compensator to close a control loop formed by the one or more bridges, external passive components, one of the ADCs of the plurality of ADCs, and one of the controllers of the plurality of controllers.

5. The integrated circuit of claim 1 , wherein each of the plurality of controllers includes a register.

6. The integrated circuit of claim 4 , wherein each of the plurality of bridges includes a register.

7. The integrated circuit of claim 1 , wherein the NVM is operable to update the plurality of configurations at power-up.

8. The integrated circuit of claim 5 , wherein the main controller is operable to copy some of the configuration information from the NVM to the respective registers of the plurality of bridges and the plurality of controllers.

9. The integrated circuit of claim 1 , wherein the main controller is coupled to the plurality of controllers and the plurality of bridges by a configuration bus.

10. The integrated circuit of claim 9 , wherein each controller of the plurality of controllers and each bridge of the plurality of bridges is coupled by a communication fabric.

11. The integrated circuit of claim 10 , wherein the communication fabric is one of: an asynchronous bus, a crossbar, a network of wires, or dedicated connections with multiplexers.

12. The integrated circuit of claim 11 , wherein each controller of the plurality of controller operates using a clock signal.

13. The integrated circuit of claim 1 , wherein the main controller is operable to configure a single controller from the plurality of controllers to operate with more than two bridges of the plurality of bridges.

14. A system comprising:
one or more power supply rails;
one or more logic units coupled to the one or more power supply rails, the one or more power supply rails to provide power supply to the one or more logic units; and
a power management integrated circuit (PMIC) coupled to the one or more power supply rails, the PMIC including:
a plurality of bridges which are operable to drive respective power supplies on the one or more power supply rails;
a plurality of controllers;
a main controller to couple one or more controllers from the plurality of controllers to one or more bridges from the plurality of bridges; and
a non-volatile memory (NVM) coupled to the main controller, the NVM to store a plurality of configurations for coupling the plurality of bridges with the plurality of controllers, the plurality of configurations including one or more of:
switching frequency for each of the plurality of bridges;
compensation filter characteristics for each of the plurality of controllers; or
coupling information for each controller and each bridge of the plurality of controllers and bridges.

15. The system of claim 14 further comprises a wireless interface for allowing the system to communicate with another device.

16. An integrated circuit comprising:
a main controller;
a register bus coupled to the main controller;
a plurality of bridges each having a register to receive configuration information from the register bus;
a plurality of controllers each having a register to receive the configuration information from the register bus; and
a non-volatile memory (NVM) coupled to the main controller, the NVM to store a plurality of configurations for coupling the plurality of bridges with the plurality of controllers, the plurality of configurations including one or more of:
switching frequency for each of the plurality of bridges;
compensation filter characteristics for each of the plurality of controllers; or
coupling information for each controller and each bridge of the plurality of controllers and bridges.

17. The integrated circuit of claim 16 further comprises:
an asynchronous bus coupled to the plurality of bridges and the plurality of controllers.

18. The integrated circuit of claim 16 , wherein the main controller is operable to provide the configuration information over the register bus for the plurality of bridges and controllers.

19. The integrated circuit of claim 16 further comprises a plurality of analog-to-digital converters (ADCs) for converting voltage levels on the one or more power supply rails to their respective digital representations.

Assignees

• Henzler Stephan
• Herbison David
• Intel Ip Corp

Inventors

• Henzler Stephan
• Herbison David

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title