Electronic device

Patent metadata

Field	Value
Publication number	US-9529714-B2
Application number	US-201414559509-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Jun 9, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An electronic device includes a semiconductor memory, and the semiconductor memory includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a ferromagnetic material with molybdenum (Mo) added thereto.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a first magnetic layer having a variable magnetization direction;
a second magnetic layer having a pinned magnetization direction; and
a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer,
wherein the second magnetic layer includes FeCoB and molybdenum (Mo) as an additive,
wherein a content of the molybdenum in the second magnetic layer is more than zero and less than 10%, and
wherein the second magnetic layer has a thickness of 10 Å to 30 Å.

2. The electronic device of claim 1 , wherein the first magnetic layer includes the ferromagnetic material, and
wherein the second magnetic layer includes the ferromagnetic material which is substantially same as that included in the first magnetic layer and further includes molybdenum.

3. The electronic device of claim 1 , wherein the variable magnetization direction of the first magnetic layer is substantially perpendicular to a surface of the first magnetic layer,
wherein the pinned magnetization direction of the second magnetic layer is substantially perpendicular to a surface of the second magnetic layer.

4. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

5. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

6. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

7. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

8. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

Assignees

• Kim Yang-Kon
• Lee Bo-Mi
• Choi Won-Joon
• Kim Guk-Cheon
• Watanabe Daisuke
• Nagamine Makoto
• Eeh Young-Min
• Ueda Koji
• Nagase Toshihiko
• Sawada Kazuya
• Sk Hynix Inc
• Toshiba Kk

Inventors

• Kim Yang-Kon
• Lee Bo-Mi
• Choi Won-Joon
• Kim Guk-Cheon
• Watanabe Daisuke
• Nagamine Makoto
• Eeh Young-Min
• Ueda Koji
• Nagase Toshihiko
• Sawada Kazuya

Classifications

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/08

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title