Line termination methods and apparatus

Patent metadata

Field	Value
Publication number	US-9529713-B2
Application number	US-201414208965-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Aug 13, 2010
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

First claim

What is claimed is:

1. A method comprising:
selecting a memory device as a termination device responsive to receiving a particular address at the memory device; and
adjusting an input impedance of the memory device responsive to receiving the particular address at the memory device.

2. The method of claim 1 , wherein selecting comprises placing the memory device in a termination mode.

3. The method of claim 1 , wherein selecting a memory device comprises selecting a memory device as a termination device for another memory device.

4. The method of claim 1 , wherein selecting a memory device comprises selecting the memory device as a termination device for itself.

5. The method of claim 1 , wherein selecting a memory device comprises monitoring signal lines of an address bus for the particular address; and selecting termination circuitry in the memory device responsive to receiving the particular address.

6. The method of claim 5 , wherein selecting termination circuitry comprises activating termination circuitry in the memory device.

7. The method of claim 6 , wherein activating termination circuitry comprises coupling a pull up resistance and/or a pull down resistance to an output driver of the memory device.

8. The method of claim 6 , wherein activating termination circuitry comprises selectively activating the termination circuitry.

9. The method of claim 8 , wherein selectively activating the termination circuitry comprises activating particular portions of the termination circuitry responsive to a termination value associated with the particular address.

10. The method of claim 1 , further comprising storing termination information associated with the particular address in the memory device.

11. The method of claim 10 , wherein the termination information comprises address information corresponding to the particular address.

12. The method of claim 11 , wherein the termination information further comprises a termination value associated with the address information.

13. The method of claim 1 , further comprising operating the memory device in a sleep mode responsive to receiving an address other than the particular address and other than an address corresponding to the memory device.

14. A method of terminating a plurality of conductors in a memory system comprising one or more memory devices coupled to the plurality of conductors, the method comprising:
receiving a selected address at each of the one or more memory devices; and
selecting termination circuitry in a particular memory device of the one or more memory devices responsive to receiving the selected address at the particular memory device;
wherein the termination circuitry is configured to adjust an impedance characteristic of the particular memory device.

15. The method of claim 14 , wherein receiving a selected address comprises receiving a first target address identifying a memory device selected from a group comprised of the particular memory device and a memory device of the memory system other than the particular memory device.

16. The method of claim 14 , wherein selecting termination circuitry further comprises activating termination circuitry to apply a particular impedance value corresponding to a termination value stored in the particular memory device.

17. The method of claim 14 , further comprising storing the selected address in the particular memory device.

18. The method of claim 17 , wherein storing the selected address further comprises storing a target address in an array of non-volatile memory cells of the particular memory device.

19. The method of claim 18 , further comprising reading the target address from the non-volatile memory array and storing the target address in a register of the particular memory device as part of an initialization operation of the particular memory device.

20. The method of claim 14 , wherein the selected address comprises a first selected address and further comprising selecting the termination circuitry in the particular memory device responsive to receiving a second selected address.

21. The method of claim 20 , further comprising storing the first selected address and the second selected address in the particular memory device.

22. The method of claim 21 , wherein storing the first selected address further comprises storing a first target address corresponding to an address of a first memory device and storing the second address further comprises storing a second target address corresponding to an address of a second memory device.

23. The method of claim 21 , further comprising storing a first termination value associated with the first selected address and storing a second termination value associated with the second selected address in the particular memory device.

24. The method of claim 23 , wherein selecting the termination circuitry further comprises activating the termination circuitry responsive to the first termination value responsive to the selected target address being received by the particular memory device and activating the termination circuitry responsive to the second termination value responsive to the second selected address being received by the particular memory device.

25. A method of operating a particular memory device coupled to an address bus and a data bus, the method comprising:
selecting termination circuitry in the particular memory device responsive to the particular memory device receiving a particular value from the address bus when the particular value matches a value stored in the memory device, wherein the particular value corresponds to a selected memory device coupled to the data bus;
wherein the termination circuitry is configured to adjust an impedance characteristic of a data node coupled to the data bus.

26. The method of claim 25 , wherein receiving a particular value from the address bus comprises receiving the particular value from the address bus that is the same physical bus as the data bus.

27. The method of claim 25 , wherein a termination value associated with the particular value is also stored in the particular memory device wherein the termination circuitry is configured to adjust the impedance of the data node responsive to the termination value.

28. The method of claim 25 , wherein the selected memory device and the particular memory device are the same memory device.

29. The method of claim 25 , wherein the selected memory device is a memory device coupled to the address and data bus which is a different memory device than the particular memory device.

30. The method of claim 25 , wherein selecting the termination circuitry further comprises activating the termination circuitry where the termination circuitry is further configured to independently adjust the impedance of each data node of the particular memory device coupled to the data bus.

31. A method of operating one or more memory devices commonly coupled by an address bus and a data bus, the method comprising:
selecting termination circuitry in a particular number of the one or more memory devices responsive to the particular number of memory devices receiving an indication that a particular memory device of the one or more memory devices is selected for a memory device operation;
wherein each of the particular number of memory devices comprises one or more die each die

Assignees

• Micron Technology Inc

Inventors

• Grunzke Terry

Classifications

• G06F12/0661 Primary

  and decentralised selection · CPC title

• H04L25/0278

  Arrangements for impedance matching · CPC title

• G11C5/00 Primary

  Details of stores covered by group G11C11/00 · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title