Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Apparatuses for managing and accessing flash memory module
US9529709B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9529709-B2 |
| Application number | US-201113113376-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2011 |
| Priority date | May 24, 2010 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.
First claim
Opening claim text (preview).
What is claimed is: 1. A controller for managing a flash memory module, comprising: a communication interface for coupling with a host device; and a processing circuit coupled with the communication interface and configured for: writing a plurality of data and associated logical addresses into multiple physical pages of multiple data blocks, recording a first address group in a first page of a first addressing block in an order based on an address order of a first set of M se…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
- G06F12/0246Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9529709B2 cover?
- A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a t…
- Who is the assignee on this patent?
- Wang Chi-Lung, Chen Chia-Hsin, Lin Chien-Cheng, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).