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Method and system for using NAND page buffers to improve the transfer buffer utilization of a solid state drive
US9529668B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9529668-B2 |
| Application number | US-201414499010-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 26, 2014 |
| Priority date | Sep 26, 2014 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
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Abstract
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A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.
First claim
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What is claimed is: 1. A method, comprising: writing a lower page data from a transfer buffer of a controller of a solid state drive to a nonvolatile memory in a solid state drive; subsequent, to writing the lower page data to the non-volatile memory, storing in the transfer buffer an upper page data received from a host; subsequent to storing the upper page data in the transfer buffer, reading the lower page data from the non-volatile memory to store in the transfer buffer as…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9529668B2 cover?
- A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional emb…
- Who is the assignee on this patent?
- Wakchaure Yogesh B, Pelster David J, Hoffman Eric L, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).