Nonvolatile storage device and operating system (OS) image program method thereof

US9529541B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9529541-B2
Application numberUS-201615040249-A
CountryUS
Kind codeB2
Filing dateFeb 10, 2016
Priority dateMar 15, 2013
Publication dateDec 27, 2016
Grant dateDec 27, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.

First claim

Opening claim text (preview).

What is claimed is: 1. A nonvolatile storage device comprising: a nonvolatile memory including a first memory area and a second memory area, each memory area including a plurality of memory cells, each of the memory cells being configurable to operate in one of high data reliability mode and low data reliability mode, the first memory area operating in the high data reliability mode and the second memory area operating in the low data reliability mode; and a memory controller including a first register, a second register and a third register, the first register configured to store reliable mode information indicating whether to support a reliable mode or not, the second register configured to store pre-soldering data information, the pre-soldering data information including size information of pre-soldering data, the third register configured to store information indicating a state of the reliable mode for programming the pre-soldering data in the nonvolatile storage device from an external device, wherein the memory controller is configured to, transmit the reliable mode information to the external device, receive the pre-soldering data information from the external device and store the pre-soldering data information into the second register, enable the reliable mode by storing a first value transmitted from the external device in the third register, receive a write command and the pre-soldering data from the external device, write the pre-soldering data into the first memory area, switch the first value of the third register into a second value and disable the write operation when an amount of the pre-soldering data transmitted from the external device is equal to the size information of pre-soldering data stored in the second register, and perform data migration of the pre-soldering data from the first memory area to the second memory area while the information stored in the third register indicates that the state of the reliable mode is disabled, wherein a number of storage bits per cell of memory cells in the first memory area is smaller than a number of storage bits per cell of memory cells in the second memory area. 2. The nonvolatile storage device of claim 1 , wherein while the information stored in the third register indicates that the state of reliable mode is enabled, the data migration of the pre-soldering data from the first memory area to the second memory area is blocked. 3. The nonvolatile storage device of claim 2 , wherein the third register comprises: a first field indicating whether the reliable mode is activated or not, wherein switching of the first value is initiated by the memory controller. 4. The nonvolatile storage device of claim 3 , wherein the memory controller switches the first value to deactivate the reliable mode when the amount of the pre-soldering data transmitted from the external device is equal to the size information of pre-soldering data stored in the second register. 5. The nonvolatile storage device of claim 1 , wherein the first register is set with the reliable mode information before the external device is connected to the nonvolatile storage device. 6. The nonvolatile storage device of claim 1 , wherein the pre-soldering data includes OS image data. 7. The nonvolatile storage device of claim 1 , wherein the size information of the pre-soldering data includes a sector count. 8. The nonvolatile storage device of claim 1 , wherein deactivating the reliable mode is performed after a surface mount technology (SMT) is applied to the nonvolatile storage device. 9. A nonvolatile storage device comprising: a nonvolatile memory including a first memory area and a second memory area, each memory area including a plurality of memory cells, each of the memory cells being configurable to operate in one of high data reliability mode and low data reliability mode, the first memory area operating in the high data reliability mode and the second memory area operating in the low data reliability mode; and a memory controller including, a first register, a second register and a third register, the first register configured to store reliable mode information indicating whether to support a reliable mode or not, and the second register configured to store pre-soldering data information, the pre-soldering data information including a size information of pre-soldering data, the third register configured to store an information indicating a state of the reliable mode for programming the pre-soldering data in the nonvolatile storage device from an external device, wherein the memory controller is configured to, receive the pre-soldering data information from the external device and store the pre-soldering data information into the second register, enable the reliable mode by storing a first value transmitted from the external device in the third register, receive a write command and the pre-soldering data from the external device, store a second value transmitted from the external device into the third register, wherein the second value indicates that the writing the pre-soldering data is completed, and perform data migration of the pre-soldering data from the first memory area to the second memory area while the information stored in the third register indicates that the state of the reliable mode is disabled, wherein a number of storage bits per cell of memory cells in the first memory area is smaller than a number of storage bits per cell of memory cells in the second memory area. 10. The nonvolatile storage device of claim 9 , wherein while the information stored in the third register indicates that the reliable mode is enabled, the data migration of the pre-soldering data from the first memory area to the second memory area is blocked. 11. The nonvolatile storage device of claim 9 , wherein the third register comprises a first field and a second field indicating whether the reliable mode is activated or not, and wherein switching of the first filed and the second field is initiated by the external device. 12. The nonvolatile storage device of claim 11 , wherein the external device switches the second field to deactivate the reliable mode after a surface mount technology (SMT) is applied to the nonvolatile storage device. 13. The nonvolatile storage device of claim 9 , wherein the nonvolatile storage device comprises an embedded multi-media card (eMMC). 14. The nonvolatile storage device of claim 9 , wherein the pre-soldering data includes OS image data. 15. The nonvolatile storage device of claim 9 , wherein the first register corresponds to a vendor specific register. 16. A nonvolatile storage device comprising: a nonvolatile memory including a first memory area and a second memory area, each memory area including a plurality of memory cells, each of the memory cells being configurable to operate in one of high data reliability mode and low data reliability mode, the first memory area operating in the high data reliability mode and the second memory area operating in the low data reliability mode; and a memory controller including a register configured to store information indicating whether a reliable mode is enabled, wherein the memory controller is configured to, enable the reliable mode by setting the register with a first value transmitted from an external device; receive a write command with pre-soldering data from the external device; write the pre-soldering data into the first memory area; set the register with a second value transmitted from the external device, when the pre-soldering data is written into the first memory area an

Assignees

Inventors

Classifications

  • G06F3/0619Primary

    in relation to data integrity, e.g. data losses, bit errors · CPC title

  • in relation to availability · CPC title

  • Migration mechanisms · CPC title

  • by changing the state or mode of one or more devices · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

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What does patent US9529541B2 cover?
A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configu…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0619. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).