Liquid crystal display

US9529231B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9529231-B2
Application numberUS-201414257460-A
CountryUS
Kind codeB2
Filing dateApr 21, 2014
Priority dateAug 26, 2013
Publication dateDec 27, 2016
Grant dateDec 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a liquid crystal display that can improve an aperture ratio and liquid crystal control ability. A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and a second substrate which face each other; a pixel electrode disposed on the first substrate; a common electrode disposed on the second substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, in which the common electrode has a first cutout having a cross shape, and the pixel electrode includes a first subpixel electrode having a rhombus shape, a second subpixel electrode surrounding the first subpixel electrode, a second cutout disposed close to and along at least one of the edges of the second subpixel electrode, and a third cutout spacing the first subpixel electrode and the second subpixel electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A liquid crystal display, comprising: a first substrate and a second substrate facing each other; a pixel electrode disposed on the first substrate; a common electrode disposed on the second substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, wherein the common electrode has a first cutout having a cross shape, and the pixel electrode comprises a first subpixel electrode having a rhomboid shape, a second subpixel electrode surrounding the first subpixel electrode, a second cutout disposed along at least one edge of the second subpixel electrode, and a third cutout between the first subpixel electrode and the second subpixel electrode. 2. The liquid crystal display of claim 1 , wherein the pixel electrode comprises a rectangular shape and the second subpixel electrode comprises a rectangular shape having an empty center in a rhomboid shape. 3. The liquid crystal display of claim 2 , wherein the first cutout overlaps two diagonals of the rhombus of the first subpixel electrode. 4. The liquid crystal display of claim 3 , wherein the first subpixel electrode has a shape of at least two connected rhombuses, and the first cutout has a shape of at least two connected crosses. 5. The liquid crystal display of claim 1 , wherein the first subpixel electrode is configured to receive a first subpixel voltage, and the second subpixel electrode is configured to receive a second subpixel voltage, the first subpixel voltage having a greater magnitude than the second subpixel voltage. 6. The liquid crystal display of claim 5 , wherein the second subpixel voltage is in a range of about 0.9 or less times the first subpixel voltage. 7. The liquid crystal display of claim 6 , wherein the second subpixel voltage is in a range of about 0.75 or about 0.85 times the first subpixel voltage. 8. The liquid crystal display of claim 1 , wherein the width of the third cutout is in a range of about 1 μm to about 8 μm. 9. The liquid crystal display of claim 8 , wherein the distance between the first substrate and the second substrate is in a range of about 2.8 μm to about 3.2 μm. 10. The liquid crystal display of claim 1 , wherein the distance between the edge of the second subpixel electrode and the second cutout is three or less times the distance between the first substrate and the second substrate. 11. The liquid crystal display of claim 10 , wherein the width of the second cutout is three or less times the distance between the first substrate and the second substrate. 12. The liquid crystal display of claim 1 , further comprising: a first alignment layer disposed on the first substrate and the pixel electrode; and a second alignment layer disposed on the second substrate and the common electrode. 13. The liquid crystal display of claim 12 , wherein the first alignment layer and the second alignment layer are vertical alignment layers, the liquid crystal layer comprises liquid crystal molecules and reactivity mesogen, and the liquid crystal molecules are arranged with pretilts. 14. The liquid crystal display of claim 12 , wherein the first alignment layer and the second alignment layer comprises an alignment material and reactive mesogen, and the first alignment layer and the second alignment layer have pretilts. 15. The liquid crystal display of claim 1 , further comprising: a gate line and a data line disposed on the first substrate; a storage electrode line disposed on the first substrate and configured to receive a constant voltage; a first thin film transistor and a second thin film transistor electrically connected to the gate line and the data line; and a third thin film transistor electrically connected to the gate line, the second thin film transistor, and the storage electrode line, wherein the first subpixel electrode is electrically connected to the first thin film transistor, and the second subpixel electrode is electrically connected to the second thin film transistor. 16. The liquid crystal display of claim 1 , further comprising: a gate line, a step-down gate line, and a data line disposed on the first substrate; a storage electrode line disposed on the first substrate and configured to receive a constant voltage; a first thin film transistor and a second thin film transistor electrically connected to the gate line and the data line; and a third thin film transistor electrically connected to the step-down gate line, the second thin film transistor, and the storage electrode line, wherein the first subpixel electrode is electrically connected to the first thin film transistor, and the second subpixel electrode is electrically connected to the second thin film transistor. 17. The liquid crystal display of claim 1 , further comprising: a gate line, a first data line, and a second data line disposed on the first substrate; a first thin film transistor electrically connected to the gate line and the first data line; and a second thin film transistor electrically connected to the gate line and the second data line, wherein the first subpixel electrode is electrically connected to the first thin film transistor, and the second subpixel electrode is electrically connected to the second thin film transistor. 18. The liquid crystal display of claim 1 , wherein the first cutout has a first part extending horizontally and a second part extending vertically. 19. The liquid crystal display of claim 18 , wherein the width of the second part is the same as or larger than the width of the first part. 20. The liquid crystal display of claim 18 , wherein the angle between the third cutout and the first part of the first cutout is in the range of about 45 degrees to about 52 degrees.

Assignees

Inventors

Classifications

  • Segmented, e.g. alpha numeric display · CPC title

  • Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

  • Physics · mapped topic

  • G02F1/1343Primary

    Electrodes {(reflective electrodes G02F1/133553)} · CPC title

  • Subdivided pixels, e.g. for grey scale or redundancy · CPC title

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What does patent US9529231B2 cover?
The present invention relates to a liquid crystal display that can improve an aperture ratio and liquid crystal control ability. A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and a second substrate which face each other; a pixel electrode disposed on the first substrate; a common electrode disposed on the second substrate; and…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/134327. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).