Electronic control circuit comprising power transistors and method for monitoring the service life of the power transistors

Patent metadata

Field	Value
Publication number	US-9529038-B2
Application number	US-201114352582-A
Country	US
Kind code	B2
Filing date	Nov 21, 2011
Priority date	Nov 21, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

An electronic control circuit for an electronically commutated motor (ECM) is disclosed. A plurality of power transistors controls the ECM, and a reference transistor is formed together with the power transistors on a common support. A control unit is configured to, in a test mode: apply a test current to the reference transistor and one of the power transistors respectively; measure a saturation voltage of the reference transistor and one of the power transistors; evaluate a saturation voltage difference between the measured saturation voltages of the reference transistor and the respective power transistor; evaluate a rate of change of saturation voltage differences between a first iteration of the test mode and a second iteration of the test mode; and determine an expected remaining service life of the power transistors based on the temperature of the support during the test mode and the rate of change of the saturation voltage differences.

First claim

The invention claimed is:

1. An electronic control circuit for an electronically commutated motor (ECM), the electronic control circuit comprising:
a plurality of power transistors that are controlled in an operating mode to control the ECM;
a reference transistor that is non-charged in the operating mode of the power transistors and is arranged or formed together with the power transistors on a common support or substrate; and
a control unit configured to, in a test mode:
apply a test current to the reference transistor and one of the power transistors respectively,
measure an associated saturation voltage of the reference transistor and an associated saturation voltage of the one of the power transistors,
evaluate a saturation voltage difference between the measured saturation voltages of the reference transistor and the respective power transistor,
evaluate a rate of change of saturation voltage differences between a first iteration of the test mode and a second iteration of the test mode, and
determine an expected remaining service life of the power transistors based on a temperature of the support during the test mode and the rate of change of the saturation voltage differences.

2. The electronic control circuit according to claim 1 , wherein the first and second iterations of the test mode are consecutive.

3. The electronic control circuit according to claim 1 , wherein, in order to be supplied with the test current, the one of the power transistors and the reference transistor may be connected to one of a constant current source and a DC voltage intermediate circuit via a resistor.

4. The electronic control circuit according to claim 1 , wherein the one of the power transistors and the reference transistor can be supplied individually and consecutively with the test current via a commutator.

5. The electronic control circuit according to claim 1 , wherein the one of the power transistors and the reference transistor can be supplied simultaneously with the test current via a multiple switch.

6. The electronic control circuit according to claim 1 , wherein the control unit is configured to store empirical values of rate of change of saturation voltage differences corresponding to stages of an aging process of the power transistors.

7. The electronic control circuit according to claim 1 , wherein the control unit is configured to display a remaining service life and to generate a warning signal for an impending failure of at least one of the power transistors.

8. The electronic control circuit according to claim 1 , wherein at least four power transistors are arranged in series in pairs on respective bridge branches, which are parallel to each other, of a bridge circuit, the saturation voltage being measured in the test mode on at least one power transistor of the pair of power transistors of each bridge branch.

9. A method for monitoring power transistors in an electronic control circuit for an electronically commutated motor (ECM), the method comprising:
measuring an associated saturation voltage for one of the power transistors and an associated saturation voltage of a reference transistor in a test mode of the electronic control circuit,
evaluating a saturation voltage difference between the measured saturation voltages of the one of the power transistors and the reference transistor, which is non-charged in an operating mode of the electronic control circuit and is arranged or formed together with the power transistors on a common support or substrate,
evaluating a rate of change of saturation voltage differences between a first iteration of the test mode and a second iteration of the test mode, and
determining expected remaining service life of the power transistors based on a temperature of the support during the test mode and the rate of change of the saturation voltage differences.

10. The method according to claim 9 , wherein the first and second iterations of the test mode are carried out consecutively.

11. The method according to claim 9 , wherein the rate of change of the saturation voltage difference is compared to stored empirical values characterizing an aging process.

12. The method according to claim 9 , wherein the method further includes selectively generating a signal for displaying one of (i) the remaining service life and (ii) an impending end to the service life of the one of the power transistors.

13. The method according to claim 9 , further comprising:
before every operation of the electronic control circuit, switching from the operating mode to the test mode; and
switching from the test mode to the operating mode subsequent to completion of the test mode.

14. The method according to claim 9 , wherein saturation voltages of each of the power transistors are measured during the test mode, wherein a rate of change of saturation voltage difference is determined with respect to each of the power transistors, and wherein a highest rate of change of the saturation voltage differences is regarded as definitive for an advance of the aging process and the expected remaining service life of the power transistors.

15. The method according to claim 14 , wherein measuring the saturation voltages of the power transistors and of the reference transistor are carried out consecutively or simultaneously.

16. The method according to claim 9 , wherein the method further includes supplying a test current to the reference transistor and the one of the power transistors from one of a constant current source and a DC voltage intermediate circuit via a resistor.

17. The method according to claim 13 further comprising, at periodic intervals during the operating mode, switching from the operating mode to the test mode.

Assignees

• Lipp Helmut
• Haas Günter
• Bürkert Martin
• Ebm Papst Mulfingen Gmbh & Co Kg

Inventors

• Lipp Helmut
• Haas Günter
• Bürkert Martin

Classifications

• G01R31/2642 Primary

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G01R31/282 Primary

  Testing of electronic circuits specially adapted for particular applications not provided for elsewhere (G01R31/2801 and G01R31/2851 take precedence) · CPC title

• H02M7/53875

  with analogue control of three-phase output · CPC title

• G01R31/42

  AC power supplies · CPC title