Randomly sampling reference ADC for calibration

Patent metadata

Field	Value
Publication number	US-9525428-B2
Application number	US-201514955905-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 17, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

First claim

What is claimed is:

1. A randomized interleaved analog-to-digital converter comprising:
two or more analog-to-digital converters to sample, interleaved in time according to a pseudo-randomized sequence, an analog input of the randomized interleaved analog-to-digital converter and generate respective digital outputs;
a digital combiner to combine the respective digital outputs of the two or more analog-to-digital converters to generate a digital output of the randomized interleaved analog-to-digital converter based on the pseudo-randomized sequence;
a reference analog-to-digital converter for randomly sampling the analog input and generating reference digital outputs that are representative of the digital outputs of the two or more analog-to-digital converters based on randomized sampling periods; and
calibration logic for measuring interleaving errors of the two-or analog-to-digital converters based on the respective digital outputs of the two-or more analog-to-digital converters and the reference digital outputs.

2. The randomized interleaved analog-to-digital converter of claim 1 , wherein each time the reference analog-to-digital converter samples the analog input, the reference analog-to-digital converter samples the analog-input along with one of the analog-to-digital converters that is sampling the analog input.

3. The randomized interleaved analog-to-digital converter of claim 1 , wherein the reference analog-to-digital converter has as sampling frequency which is spread out across a range of frequencies.

4. The randomized interleaved analog-to-digital converter of claim 1 , further comprising:
a clock generator for generating a clock signal having a range of clock periods for the reference analog-to-digital converter to randomly sample the analog input.

5. The randomized interleaved analog-to-digital converter of claim 1 , further comprising:
one or more clock divider circuits that output an edge of a clock signal for driving the reference analog-to-digital converter to sample the analog input every X number of clock cycles of an input clock; and
a randomization engine to randomize X used by the one or more clock divider circuits.

6. The randomized interleaved analog-to-digital converter of claim 1 , wherein:
a first resolution of any one of the two or more analog-to-digital converters is higher than a second resolution of the reference analog-to-digital converter.

7. The randomized interleaved analog-to-digital converter of claim 1 , wherein the reference analog-to-digital converter serves as an additional signal path for converting the analog input signal in parallel with the two or more analog-to-digital converters.

8. A method for calibrating a randomized interleaved analog-to-digital converter comprising:
generating, by a clock generator, first clock signals for controlling two or more analog-to-digital converters of the randomized time-interleaved analog-to-digital converter to sample, interleaved in time according to a pseudo-randomized sequence, an analog input of the randomized time-interleaved analog-to-digital converter;
generating, by the clock generator, a second clock signal for triggering a reference analog-to-digital converter to randomly sample the analog input and generate digital outputs at randomized periods, wherein, when the reference analog-to-digital converter samples the analog input, one of the two or more analog-to-digital converters is also sampling the analog input at substantially the same time;
processing respective digital outputs of the two or more analog-to-digital converters and the digital outputs of the reference analog-to-digital converter over a period of time to generate measurements; and
determining interleaving errors associated with the two or more analog-to-digital converters based on the measurements.

9. The method of claim 8 , wherein processing respective digital outputs of the two or more analog-to-digital converters and digital outputs of the reference analog-to-digital converter to generate measurements comprises:
for each one of the two or more analog-to-digital converters, determining a mean of differences between digital outputs of a particular analog-to-digital converter and corresponding digital outputs of the reference analog-to-digital converter generated when the reference analog-to-digital converter is sampling along the particular analog-to-digital converter.

10. The method of claim 9 , wherein determining interleaving errors comprises updating an offset correction term for the particular analog-to-digital converter based on the mean.

11. The method of claim 8 , wherein processing respective digital outputs of the two or more analog-to-digital converters and digital outputs of the reference analog-to-digital converter to generate measurements comprises:
for each one of the two or more analog-to-digital converters, determining a mean of differences between magnitudes of digital outputs of a particular analog-to-digital converter and magnitudes of corresponding digital outputs of the reference analog-to-digital converter generated when the reference analog-to-digital converter is sampling along the particular analog-to-digital converter.

12. The method of claim 11 , wherein determining interleaving errors comprises updating an interleaving gain correction term for the particular analog-to-digital converter based on the mean.

13. The method of claim 8 , wherein processing respective digital outputs of the two or more analog-to-digital converters and digital outputs of the reference analog-to-digital converter over a period of time to generate measurements comprises:
for each one of the two or more analog-to-digital converters, determining a cross correlation of a first signal representing digital outputs of a particular analog-to-digital converter and a second signal representing digital outputs of the reference analog-to-digital converter generated when the reference analog-to-digital converter is sampling along the particular analog-to-digital converter.

14. The method of claim 13 , wherein determining interleaving errors comprises updating an interleaving skew correction term for the particular analog-to-digital converter based on the cross correlation of the first signal and the second signal.

15. The method of claim 13 , wherein the digital outputs of the particular analog-to-digital converter and the digital outputs of the reference analog-to-digital converter are represented by a single bit.

16. A randomized converter system on a single chip for converting an analog input to a digital output, the system comprising:
two or more analog-to-digital converters to sample, interleaved in time according to a pseudo-randomized sequence, the analog input of the randomized converter system and generate respective digital outputs;
a reference analog-to-digital converter for sampling the analog input along with one of the two or more analog-to-digital converters at random and generating reference digital outputs according to randomized sampling periods; and
logic for recording measurements of digital outputs of the two or more analog-to-digital converters and the reference digital outputs of the reference analog-to-digital converter; and
an microprocessor on-chip with the two or more analog-to-digital converters for assisting the randomized converter system based on the measurements.

17. The randomized converter system of claim 16 , further comprising:
a clock generator for generating clock signals to the two or more analog-to-digital converters to sample, interleaved in time according to the pseudo-ra

Assignees

• Analog Devices Inc

Inventors

• Devarajan Siddharth
• Otte Eric
• Rakuljic Nevena
• Speir Carroll C

Classifications

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• H03M3/382

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/1028

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/1019 Primary

  by storing a corrected or correction value in a digital look-up table · CPC title