Input circuit

Patent metadata

Field	Value
Publication number	US-9525404-B2
Application number	US-201414476217-A
Country	US
Kind code	B2
Filing date	Sep 3, 2014
Priority date	Jan 27, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

The input circuit includes a first switch control circuit that controls a first switch and a second switch. The first switch control circuit turns off the first switch and the second switch in a first period during which a first input signal and a second input signal are DC signals. The first switch control circuit turns on the first switch and the second switch in a second period during which the first input signal and the second input signal are AC signals.

First claim

What is claimed is:

1. An input circuit comprising:
a first input terminal that receives a first input signal;
a second input terminal that receives a second input signal that is phase-reversed from the first input signal;
a first capacitor with a first end connected to the first input terminal and a second end connected to a first node;
a second capacitor with a first end connected to the second input terminal and a second end connected to a second node;
a reference voltage generating circuit that generates a reference voltage and supplies the voltage to a reference node;
a first resistor connected between the first node and the reference node;
a second resistor connected between the second node and the reference node;
a first switch connected in series with the first resistor between the first node and the reference node;
a second switch connected in series with the second resistor between the second node and the reference node;
a differential receiving circuit with a first input connected to the first node and a second input connected to the second node, the differential receiving circuit receiving differential signals inputted to the first input and the second input and outputting a single-phase output signal;
a first switch control circuit that controls the first switch and the second switch;
a first signal detecting circuit that receives the first input signal through the first input terminal and the second input signal through the second input terminal, and outputs a first detection signal based on the first input signal and the second input signal; and
a second signal detecting circuit that receives the output signal of the differential receiving circuit and outputs a second detection signal based on the output signal,
wherein the first switch control circuit turns off the first switch and the second switch in a first period during which the first input signal and the second input signal are DC signals, and
the first switch control circuit turns on the first switch and the second switch in a second period during which the first input signal and the second input signal are AC signals,
wherein the first signal detecting circuit outputs the first detection signal when the first signal detecting circuit detects that the first input signal and the second input signal are the DC signals, and
the first switch control circuit turns off the first switch and the second switch in response to the first detection signal, and
wherein the second signal detecting circuit outputs the second detection signal when the second signal detecting circuit detects that the output signal is the AC signal, and
the first switch control circuit turns on the first switch and the second switch in response to the second detection signal.

2. The input circuit according to claim 1 , wherein the DC signal contains at least a prespecified number of consecutive identical bits in a preset specified period, and
the AC signal contains a smaller number of consecutive identical bits than the prespecified number in the preset specified period.

3. The input circuit according to claim 2 , wherein the AC signal has a one-to-one ratio of “1” and “0” in the preset specified period.

4. An input circuit comprising:
a first input terminal that receives a first input signal;
a second input terminal that receives a second input signal that is phase-reversed from the first input signal;
a first capacitor with a first end connected to the first input terminal and a second end connected to a first node;
a second capacitor with a first end connected to the second input terminal and a second end connected to a second node;
a reference voltage generating circuit that generates a reference voltage and supplies the voltage to a reference node;
a first resistor connected between the first node and the reference node;
a second resistor connected between the second node and the reference node;
a first switch connected in series with the first resistor between the first node and the reference node;
a second switch connected in series with the second resistor between the second node and the reference node;
a differential receiving circuit with a first input connected to the first node and a second input connected to the second node, the differential receiving circuit receiving differential signals inputted to the first input and the second input and outputting a single-phase output signal;
a first switch control circuit that controls the first switch and the second switch;
a third switch connected between the first input terminal and the first end of the first capacitor;
a fourth switch connected between the second input terminal and the first end of the second capacitor;
a third resistor with a first end connected to the first input terminal;
a fourth resistor with a first end connected to the second input terminal and a second end connected to a second end of the third resistor;
a fifth resistor with a first end connected to the second end of the third resistor;
a fifth switch with a first end connected to a second end of the fifth resistor and a second end connected to the first end of the first capacitor;
a sixth switch with a first end connected to the second end of the fifth resistor and a second end connected to the first end of the second capacitor; and
a second switch control circuit that controls the third switch, the fourth switch, the fifth switch, and the sixth switch,
wherein the first switch control circuit turns off the first switch and the second switch in a first period during which the first input signal and the second input signal are DC signals, and
the first switch control circuit turns on the first switch and the second switch in a second period during which the first input signal and the second input signal are AC signals, and
wherein the second switch control circuit turns on the third switch and the fourth switch and turns off the fifth switch and the sixth switch in a period during which the first input signal and the second input signal are fixed signals constituting the DC signals immediately before the second period in the first period, and in the second period, and
the second switch control circuit turns off the third switch and the fourth switch and turns on the fifth switch and the sixth switch in a period during which the first input signal and the second input signal are inversion signals constituting the DC signals in the first period.

5. The input circuit according to claim 4 , further comprising a first signal detecting circuit that receives the first input signal through the first input terminal and the second input signal through the second input terminal, and outputs a first detection signal based on the first input signal and the second input signal,
wherein the first signal detecting circuit outputs the first detection signal when the first signal detecting circuit detects that the first input signal and the second input signal are fixed signals immediately before the second period, and
the first switch control circuit turns off the first switch and the second switch in response to the first detection signal.

6. The input circuit according to claim 5 , wherein the second switch control circuit turns off the third switch and the fourth switch and turns on the fifth switch and the sixth switch before the first detection signal is outputted from the first signal detecting circuit, and
the second switch control circuit turns on the third switch and the fourth switch and turns off the fifth switch and the sixth switch in response to the first detection signal.

7. The input circuit according to claim 6 , wherein the DC signal contains at least a prespecified number of consecutive identical bits in a preset specified period, and
the AC si

Assignees

• Toshiba Kk

Inventors

• Terauchi Ryota
• Fujii Shinsuke

Classifications

• H03K19/017563

  with at least one differential stage · CPC title

• H03K5/086

  generated by feedback · CPC title

• H03K19/017545

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K19/017527

  with at least one differential stage · CPC title

• H03K5/003 Primary

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title