Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9525128-B2
Application number	US-201414225401-A
Country	US
Kind code	B2
Filing date	Mar 25, 2014
Priority date	May 22, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a material layer on a substrate;
performing a selective oxidation process on an exposed surface of the material layer, wherein the exposed surface of the material layer comprises a first surface and a second surface, and wherein the first surface of the material layer is selectively oxidized to form a capping oxide layer and the second surface of the material layer is not oxidized during the selective oxidation process;
etching the material layer through the second surface of the material layer using the capping oxide layer as an etch mask to form a material pattern;
forming a lower pattern on the substrate before forming the material layer,
wherein the material layer is formed to cover a top surface and at least a portion of a sidewall of the lower pattern;
wherein the first surface of the material layer covers the top surface of the lower pattern;
wherein the second surface of the material layer covers at least a portion of the sidewall of the lower pattern; and
wherein the material pattern is formed on the top surface of the lower pattern.

2. The method of claim 1 , wherein the material layer on the top surface of the lower pattern is thicker than the material layer on the sidewall of the lower pattern.

3. The method of claim 1 , wherein the selective oxidation process is an anisotropic oxidation process having a specific oxidation direction; and
wherein the first surface of the material layer is exposed in the specific oxidation direction and the second surface of the material layer is not exposed in the specific oxidation direction in the selective oxidation process.

4. The method of claim 1 , wherein the material layer is etched by an isotropic etching process.

5. The method of claim 4 , wherein the isotropic etching process is a wet etching process.

6. A method of manufacturing a semiconductor device, the method comprising:
forming a lower electrode on a substrate;
forming a conductive layer having a first surface covering a top surface of the lower electrode and a second surface covering at least a portion of a sidewall of the lower electrode;
performing a selective oxidation process to form a capping oxide layer on a first surface of the conductive layer, wherein a second surface of the conductive layer is not oxidized; and
etching the conductive layer through the second surface of the conductive layer to form an upper electrode on the top surface of the lower electrode,
wherein an etch rate of the capping oxide layer is less than an etch rate of the conductive layer when the conductive layer is etched.

7. The method of claim 6 , wherein the selective oxidation process is an anisotropic oxidation process having an oxidation direction substantially perpendicular to a top surface of the substrate.

8. The method of claim 7 , wherein the anisotropic oxidation process includes at least one of an anisotropic plasma oxidation process or an anisotropic thermal oxidation process.

9. The method of claim 6 , wherein the conductive layer is etched by an isotropic etching process.

10. The method of claim 9 , wherein the isotropic etching process is a wet etching process.

11. The method of claim 6 , further comprising:
forming a data storage layer covering the top surface and at least a portion of the sidewall of the lower electrode before forming the conductive layer,
wherein the conductive layer is formed on the data storage layer.

12. The method of claim 11 , further comprising:
forming a protection insulating spacer surrounding the sidewall of the lower electrode before forming the data storage layer.

13. The method of claim 12 , wherein forming the protection insulating spacer comprises:
conformally forming a protection insulating layer on the substrate having the lower electrode; and
performing an etch-back process on the protection insulating layer to form the protection insulating spacer.

14. The method of claim 11 , wherein the data storage layer includes a first magnetic layer, a tunnel barrier layer, and a second magnetic layer that are sequentially stacked; and
wherein one of the first and second magnetic layers has a magnetization direction fixed in one direction, and the other of the first and second magnetic layers has a magnetization direction changeable between a parallel direction and an anti-parallel direction with respect to the fixed magnetization direction.

15. The method of claim 11 , further comprising:
etching the data storage layer disposed on the sidewall of the lower electrode to form a data storage part after forming the upper electrode.

16. The method of claim 15 , wherein the data storage layer is etched by an anisotropic etching process having a tilted etching direction with respect to a top surface of the substrate.

17. The method of claim 6 , wherein the conductive layer on the top surface of the lower electrode is thicker than the conductive layer on the sidewall of the lower electrode.

18. The method of claim 6 , wherein the conductive layer is a metal containing layer; and
wherein the conductive layer is etched using an etchant having a pH of between about 5 to about 7.

Assignees

• Chung Sungyoon
• Bae Jinhye
• Kwon Hyungjoon
• Park Jongchul
• Lee Wonjun
• Samsung Electronics Co Ltd

Inventors

• Chung Sungyoon
• Bae Jinhye
• Kwon Hyungjoon
• Park Jongchul
• Lee Wonjun

Classifications

• H10N50/80 Primary

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10B12/01 Primary

  Manufacture or treatment · CPC title