TFT, mask for manufacturing the TFT, array substrate and display device
US-8952384-B2 · Feb 10, 2015 · US
Array substrate, method for manufacturing the same, and display device
US9525075B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9525075-B2 |
| Application number | US-201615098398-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 14, 2016 |
| Priority date | May 13, 2015 |
| Publication date | Dec 20, 2016 |
| Grant date | Dec 20, 2016 |
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- Title
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Abstract
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An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode. A length of a shortest distance on the semiconductor layer from the first connection point to the second connection point may be no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode.
First claim
Opening claim text (preview).
What is claimed is: 1. An array substrate, comprising: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed, wherein the semiconductor layer is connected to the source electrode and the drain electr…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9525075B2 cover?
- An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has …
- Who is the assignee on this patent?
- Boe Technology Group Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).