Vertical high-voltage MOS transistor and method of forming the same

Patent metadata

Field	Value
Publication number	US-9525035-B2
Application number	US-201414563706-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 8, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

First claim

What is claimed is:

1. A MOS transistor comprising:
a semiconductor substrate having a top surface and a bottom surface;
a drain drift region positioned above the bottom surface of the semiconductor substrate;
a body region positioned above the drain drift region;
low density drain (LDD) regions positioned above the drain drift region and each of the LDD regions having a lower implant dosage than the body region; and
a trench structure extending from the top surface of the semiconductor substrate to the drain drift region, the trench structure having a first side wall and a second side wall facing away from the first side wall, the first side wall abutting the body region and free from contacting any of the LDD regions, and the second side wall abutting one of the LDD regions.

2. The MOS transistor of claim 1 , further comprising:
a drain region positioned below the drain drift region, the drain region having a first dopant concentration,
wherein each of the LDD regions has a second dopant concentration less than the first dopant concentration.

3. The MOS transistor of claim 1 , further comprising:
a body contact region positioned within the body region, the body contact region having a greater dopant concentration than the body region,
wherein the first side wall of the trench structure abutting the body contact region, and
wherein the second side wall of the trench structure faces away from the body contact region and the body region.

4. The MOS transistor of claim 3 , further comprising:
a source region positioned within the body region and above the body contact region; and
a source-body metal contact contacting source region and the body contact region.

5. The MOS transistor of claim 1 , further comprising:
a gate dielectric layer positioned above the top surface of the semiconductor substrate and the body region; and
a gate electrode positioned on the gate dielectric layer above the body region.

6. The MOS transistor of claim 1 , wherein the trench structure includes a conductive field plate and a non-conductive liner insulating the conductive field plate from the drain drift region, one of the LDD regions, and the body region.

7. The MOS transistor of claim 1 , wherein the trench structure includes a field plate with a conductive type of the body region.

8. The MOS transistor of claim 1 , wherein the trench structure includes:
a lower conductive field plate;
an upper conductive field plate spaced apart from the lower conductive field plate; and
a non-conductive liner insulating the lower conductive field plate and the upper conductive field plate from drain drift region, one of the LDD regions, and the body region.

9. The MOS transistor of claim 1 , further comprising:
a conductive field plate positioned in the trench structure;
a body contact region positioned within the body region;
a source region positioned within the body region and above the body contact region; and
a source-body metal contact contacting the body contact region, the source region, and the conductive field plate in the trench structure.

10. The MOS transistor of claim 1 , further comprising:
a perimeter trench structure laterally surrounding the trench structure and the body region.

11. A method of forming a MOS transistor, the method comprising:
forming a drain drift region positioned above a bottom surface of a semiconductor substrate;
forming a body region positioned above the drain drift region;
forming low density drain (LDD) regions positioned above the drain drift region and each of the LDD regions having a lower implant dosage than the body region; and
forming a trench structure extending from the top surface of the semiconductor substrate to the drain drift region, the trench structure having a first side wall and a second side wall facing away from the first side wall, the first side wall abutting the body region and free from contacting any of the LDD regions, and the second side wall abutting one of the LDD regions.

12. The method of claim 11 , further comprising:
forming a drain region below the drain drift region, the drain region having a first dopant concentration,
wherein each of the LDD regions has a second dopant concentration less than the first dopant concentration.

13. The method of claim 11 , further comprising:
forming a body contact region within the body region, the body contact region having a greater dopant concentration than the body region,
wherein the first side wall of the trench structure abutting the body contact region, and
wherein the second side wall of the trench structure faces away from the body contact region and the body region.

14. The method of claim 13 , further comprising:
forming a source region within the body region and above the body contact region; and
a source-body metal contact contacting the source region and the body contact region.

15. The method of claim 11 , further comprising:
forming a gate dielectric layer above the top surface of the semiconductor substrate and the body region; and
forming a gate electrode on the gate dielectric layer above the body region.

16. The method of claim 11 , wherein the trench structure includes a conductive field plate and a non-conductive liner insulating the conductive field plate from the drain drift region, one of the LDD regions, and the body region.

17. The method of claim 11 , wherein the trench structure includes a field plate with a conductive type of the body region.

18. The method of claim 11 , wherein the trench structure includes:
a lower conductive field plate;
an upper conductive field plate spaced apart from the lower conductive field plate; and
a non-conductive liner insulating the lower conductive field plate and the upper conductive field plate from drain drift region, one of the LDD regions, and the body region.

19. The method of claim 11 , further comprising:
forming a conductive field plate in the trench structure;
forming a body contact region within the body region;
forming a source region within the body region and above the body contact region; and
forming a source-body metal contact contacting the body contact region, the source region, and the conductive field plate in the trench structure.

20. The method of claim 11 , further comprising:
forming a perimeter trench structure laterally surrounding the trench structure and the body region.

21. A MOS transistor comprising:
a semiconductor substrate having a top surface and a bottom surface;
a drain drift region positioned above the bottom surface of the semiconductor substrate;
a body region positioned above the drain drift region;
a body contact region positioned within the body region, the body contact region having a greater dopant concentration than the body region;
a low density drain (LDD) region positioned above the drain drift region and each of the LDD regions having a lower implant dosage than the body region; and
a trench structure extending from the top surface of the semiconductor substrate to the drain drift region, the trench structure having:
a first side wall abutting the body region and the body contact region; and
a second side wall abutting the LDD region and faces away from the first side wall, the body contact region and the body region.

22. A method of forming a MOS transistor, the method comprising:
forming a drain drift region above a bottom surface of a semiconductor substrate;
forming a body region above the drain d

Assignees

• Texas Instruments Inc

Inventors

• Kocon Christopher Boguslaw
• Molloy Simon John
• Neilson John Manning Savidge
• Kawahara Hideaki

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10D84/141

  VDMOS having built-in components · CPC title